Jump to content
IGNORED

Civility


wdw

Recommended Posts

10 minutes ago, Samuel T Cogley said:

 

Am I the only one noticing that a thread about civility is really a thread about "feeling vs. knowing", and those who "feel" are the ones demanding civility? 

 

 

No.

 

There does seem to be a correlation between those demanding "civility", creepy stalking behavior, and occasional overt threats.

Link to comment
On 9/27/2012 at 6:50 AM, jhwalker said:

 

I agree it's amazing, but I saw the exact opposite - so not so f-ing simple, after all.

 

Particularly in this thread, the malice and ganging-up has come almost exclusively from the so-called "subjectivists" - in fact, there's a whole page or so that is nothing but ganging up on the poor "propeller-heads", lots of venom about people who have more ego than brains, etc.

 

The lack of civility has been quite firmly on the subjectivist side of the street :/

 

Amazing, for sure.

 

Fortunately, we are in a new political era now, where truth and honest good-will prevail, so all of this has changed for the better.

Link to comment
2 hours ago, plissken said:

In my case I've done my homework. Including when you posted a paper attempting to bolster your point about bits not being bits and I quoted the section about clock domain boundaries being best done using FIFO buffers.

 

Haha! Perhaps you missed the intention of my point then? I never suggested that bits shouldn't be bits in that, certainly treating digital information as 1s and 0s is critical. I am certain that not all indeterminate phase clock domains are not crossed using FIFO buffers, indeed PLL is probably the norm, and so there can be artifacts. Corners are cut all over the place in order to meet price specifications. You know a $100 DAC can't have $200 in parts.

 

In any case these are the issues that can be discussed back and forth in a technical fashion. That's all good discussion.

Custom room treatments for headphone users.

Link to comment
4 hours ago, Ralf11 said:

delusional might have both a common meaning and a DSM meaning - dunno

 

Yes! of course there is the "Social (Pragmatic) Communication Disorder" diagnosis in the new DSM (5) ;) 

Custom room treatments for headphone users.

Link to comment
4 hours ago, Samuel T Cogley said:

 

In my experience on audiophile forums, the thought process goes something like this:

 

"Science can't explain why I believe A sounds better than B, ergo, I'm free to dismiss science and ignore the concepts of expectation and confirmation bias.  Besides, like ML says, audio is supposed to be fun".

 

I find that variations on this are more or less the "subjectivists mantra", to use a term popular on the forum ("subjectivists").  In a thread from several months ago, I seem to remember something like "feeling vs. knowing", which may be more descriptive, but still doesn't totally fit.

 

Am I the only one noticing that a thread about civility is really a thread about "feeling vs. knowing", and those who "feel" are the ones demanding civility?  I've said before that audio gear to me is the same as the toaster or vacuum cleaner.  But some apparently "feel" their gear.

 

And before someone airs out the old, "skeptics don't like listening to music" trope, I listen to music at least 3-4 hours per day, every day.  And I quite enjoy it.

 

 

 

To my mind, you seem somewhat paranoid.

 

Though I do wonder why you need to humiliate people...from your post.

 

"But some apparently "feel" their gear."  

 

Really, Coggly Dimwit?..that is just purely insulting...hey and that, my comment, on a civility thread I started.

 

"really a thread about "feeling vs. knowing", and those who "feel" are the ones demanding civility?"

 

Seriously, you need to get out a bit more.  And, of course, the "knowing" is all on your side...absolutely charming...you're just a wonderful guy.

Link to comment
2 hours ago, jabbr said:

 

Haha! Perhaps you missed the intention of my point then? I never suggested that bits shouldn't be bits in that, certainly treating digital information as 1s and 0s is critical. I am certain that not all indeterminate phase clock domains are not crossed using FIFO buffers, indeed PLL is probably the norm, and so there can be artifacts. Corners are cut all over the place in order to meet price specifications. You know a $100 DAC can't have $200 in parts.

 

In any case these are the issues that can be discussed back and forth in a technical fashion. That's all good discussion.

 

Find me an Ethernet PHY, PCIe bus, RAM bus, CPU L3/2/1 cache, USB bus that is PLL and then I'll agree. 

Link to comment
17 minutes ago, plissken said:

 

Find me an Ethernet PHY, PCIe bus, RAM bus, CPU L3/2/1 cache, USB bus that is PLL and then I'll agree. 

 

Well look you can read just as easily as I can but offhand ... https://www.microsemi.com/document-portal/doc_view/126475-the-basics-of-synchronized-ethernet-synce

 

http://www.analog.com/media/en/technical-documentation/application-notes/EE-269.pdf

 

I mean the number of implementations are endless...

Custom room treatments for headphone users.

Link to comment
2 hours ago, jabbr said:

 

Well look you can read just as easily as I can but offhand ... https://www.microsemi.com/document-portal/doc_view/126475-the-basics-of-synchronized-ethernet-synce

 

http://www.analog.com/media/en/technical-documentation/application-notes/EE-269.pdf

 

I mean the number of implementations are endless...

 

From the linked article:

 

However, Ethernet equipment designers often lack in-depth understanding of synchronization and may underestimate
the complexity of the issue.A common assumption is synchronization over Ethernet can be
achieved merely by replacing the free-running crystal oscillator used for Ethernet Physical Layer Device
(PHY) with a general purpose synchronization device (PLL).Certainly, this is not the case
and designs based on such anassumption are destined to fail.
 
 
Also this from the same article you linked to (and is supports my claim about
MIXED signalling systems):
 
Any Gigabit or 10GbE PHY
device should be able to support
synchronized Ethernet, so long
as it provides a recovered clock
on one of its output pins. The
recovered clock is cleaned by the
PLL and fed to the 25MHz crystal
oscillator input pin on the PHY
device. Some new Ethernet PHY
devices provide a dedicated pin
for the synchronization input. The
advantage of this approach is that
frequency input can be higher
than 25MHz—higher clock fre
-
quencies usually have lower jitter.
In addition, this approach avoids
any potential timing loop prob
 
This is talking about link to link to link Ethernet. I'm talking about Ethernet PHY over to
PCIe or USB bus.
 
The 25MHz referred to is what is a common clock for Ethernet PHY's and then clock
multiplied from there.
 
Again we are talking about clock domain boundaries between these systems and:
 
Find me an Ethernet PHY, PCIe bus, RAM bus, CPU L3/2/1 cache, USB bus that is
PLL *for clock domain boundary crossing* and then I'll agree. 
 
 
Link to comment
8 hours ago, jabbr said:

 

Haha! Perhaps you missed the intention of my point then? I never suggested that bits shouldn't be bits in that, certainly treating digital information as 1s and 0s is critical. I am certain that not all indeterminate phase clock domains are not crossed using FIFO buffers, indeed PLL is probably the norm, and so there can be artifacts. Corners are cut all over the place in order to meet price specifications. You know a $100 DAC can't have $200 in parts.

 

In any case these are the issues that can be discussed back and forth in a technical fashion. That's all good discussion.

 

It is possible for $5000 DACs to have $200 in parts.  

And always keep in mind: Cognitive biases, like seeing optical illusions are a sign of a normally functioning brain. We all have them, it’s nothing to be ashamed about, but it is something that affects our objective evaluation of reality. 

Link to comment
8 hours ago, plissken said:
Again we are talking about clock domain boundaries between these systems and:
 
Find me an Ethernet PHY, PCIe bus, RAM bus, CPU L3/2/1 cache, USB bus that is
PLL *for clock domain boundary crossing* and then I'll agree

 

Agree, don’t agree ... This is a moving target. I’m unsure what overall point you are trying to make. I have always said that FIFO should be used *for clock  domain crossing*. (Search my multiple posts on this) Google for a few seconds and do your own reading.

 

When using PLL you may synch not cross the clock domain and this can lead to higher jitter. This gets technical and waaaay OT here. There are countless examples. 

 

If if you are interested in actually implementing eg an Ethernet interface, Xilinx’s Vivado has a free version that you can download and do a lot with. 

Custom room treatments for headphone users.

Link to comment

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now



×
×
  • Create New...