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Discrete DSD DAC - Definition


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Have you found Jussi's (Miska) DSC 1 DAC design descriptions here on CA? Discrete DAC should mean DAC chip-less, using only discrete components in an analog low pass filter. No Sabre, TI, etc. DAC chip or FPGA approach. Unless someone is bastardizing the use of the term Discrete DAC. LOL

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I know what a NOS (non over sampling) DAC is, also a ladder DAC, but a discrete DSD DAC I don't know.

 

What's the architecture of a discrete DAC, is it chipless in some way, sans ESS90xx ?

 

As above the DSC1 is a great example, and the design is published and open so people can see the actual circuit.

 

In the same way that an opamp can be built from a discrete design (transistors, resistors, capacitors), a DSD DAC can very easily be built from discrete components that anyone can buy and even wire together without a circuit board.

 

The DSD signal has three wires:

1) BCLK -- the clock which runs at a multiple of 44.1/48 (DSD64 is 64x)

2) DSDR -- the right data

3) DSDL -- the left data

 

So, the very simplest design is to take the DSDR/L signals, buffer with a flip-flop and then place some type of analog low-pass filter to filter out the background BCLK. Now with DSD512 this is 22 Mhz, so an analog LPF at 100 khz pole can more easily filter out the BCLK and its ultrasonic noise.

 

Next up in complexity, you can use a D-flipflop, gated by BCLK, and this will output DSDR and DSDR', so you have a very simple balanced signal to which the filters can be applied.

 

What DSC1 does is apply a very simple FIR filter composed of shift registers, and this gets us up to the next level of complexity, which for illustrative purposes is very helpful, so bear with me:

The BCLK gates a set of shift registers which clock in the DSDR/L signals and provide a set of output signals, each having a logic level: 5V or 3.3V depending on the type of logic.

 

By placing an output resistance on the output logic level, this will provide a running "last 32 clock samples" but even when they are all "1" the voltage will never exceed logic (say 5V), and never go below ground. On the other hand given the number of samples which are switched "on", there will be a different output impedance, or current.

 

The next stage is a method to convert this variable output impedance to voltage or I-V: current to voltage. This can be done with an opamp, or discrete design itself. Borbely published a famous jFet I-V design, and then Nelson Pass greatly simplified it into the "Zen I-V" if people want to google, it is a very simple circuit itself.

 

Following the I-V stage is placed an analog filter, often a Sallen-Key lowpass design (which is 2nd order), two of which can be used to get a 4th order low pass filter -- getting rid of the 22Mhz electronic hash. This similarly can be implemented as either an opamp or discrete design and could be either tube or transistor based.

 

So yes this can be entirely chipless comprised of individual transistors or tubes, resistors and capacitors, or can contain logic chips and opamps or any mixture in between.

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Thank you jabbr and solstice380. I have seen DSC1 DAC at CA and I can follow some of the circuit, with jabbr's detail the pieces now fit together. So, why doesn't such a simple circuit gain more traction? Is it the filtering that needs to be completed prior to the DAC that Miska incorporates in HQPlayer?

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Yes HQPlayer does the filtering in software.

 

I think the idea is gaining traction, Lampizator, T+A (only Germans can do this with straight face :) ... on the DIY there is activity, but, for example I've been delayed in actually building the modifications that I've designed because I've been very backed up with projects (this being a hobby :)

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Yes the DSC1 is quite good but maybe "clinical" sounding? Certainly great for an initial design with entirely off the shelf parts, and good enough that worth improving.

 

Balancing the DSC1 can be done with a d-flop, perhaps replace I-V with discrete, :

 

 

http://www.diyaudio.com/forums/showthread.php?p=4633856, and discrete JFet SK filters

 

Also upgrade clock, and improve DSD signal isolation from USB input converter.

 

Ultimately provide direct fiber optic Ethernet to DSD output running NAA on embedded ARM with FPGA handling DSD timing from DAC's clocks...

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Yes the DSC1 is quite good but maybe "clinical" sounding? Certainly great for an initial design with entirely off the shelf parts, and good enough that worth improving.

 

Balancing the DSC1 can be done with a d-flop, perhaps replace I-V with discrete, :

 

 

Zen -> Cen -> Sen, evolution of a minimalistic IV Converter - Page 182 - diyAudio, and discrete JFet SK filters

 

Also upgrade clock, and improve DSD signal isolation from USB input converter.

 

Ultimately provide direct fiber optic Ethernet to DSD output running NAA on embedded ARM with FPGA handling DSD timing from DAC's clocks...

 

Very cool...when do you have time to make one for me? ;)) I think this is a great idea and I hope, this is where we are heading. I mentioned to Ted awhile ago about just having a DSD only dac with HQP would be awesome and simple. Interesting thread guys.

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As above the DSC1 is a great example, and the design is published and open so people can see the actual circuit.

 

Very cool description, jabbr.

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Balancing the DSC1 can be done with a d-flop, perhaps replace I-V with discrete,

 

And even with tubes :P

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I'll get working on it tonight after I get the VHDL code working ;)

 

Hope you're getting the VHDL chops ready for dabbling with the SFP integration.

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I mentioned to Ted awhile ago about just having a DSD only dac with HQP would be awesome and simple. Interesting thread guys.

 

One day people will understand that Miska was years ahead of everybody in foreward thinking.

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And even with tubes :P

 

The analog filter stage could certainly be tubed. I am treating the design as modular so you can swap in USB->DSD or SFP->DSD, for example, and then place an isolation, fifo and reclock stage, then the DSC logic etc.

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Hope you're getting the VHDL chops ready for dabbling with the SFP integration.

 

Exactly. Using zynq 7020. sfp/sgmii core -> processor which runs NAA/networkaudiod -> alsa driver -> DSD logic core -> GPIO pins.

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As above the DSC1 is a great example, and the design is published and open so people can see the actual circuit.

 

In the same way that an opamp can be built from a discrete design (transistors, resistors, capacitors), a DSD DAC can very easily be built from discrete components that anyone can buy and even wire together without a circuit board.

 

The DSD signal has three wires:

1) BCLK -- the clock which runs at a multiple of 44.1/48 (DSD64 is 64x)

2) DSDR -- the right data

3) DSDL -- the left data

 

So, the very simplest design is to take the DSDR/L signals, buffer with a flip-flop and then place some type of analog low-pass filter to filter out the background BCLK. Now with DSD512 this is 22 Mhz, so an analog LPF at 100 khz pole can more easily filter out the BCLK and its ultrasonic noise.

 

Next up in complexity, you can use a D-flipflop, gated by BCLK, and this will output DSDR and DSDR', so you have a very simple balanced signal to which the filters can be applied.

 

What DSC1 does is apply a very simple FIR filter composed of shift registers, and this gets us up to the next level of complexity, which for illustrative purposes is very helpful, so bear with me:

The BCLK gates a set of shift registers which clock in the DSDR/L signals and provide a set of output signals, each having a logic level: 5V or 3.3V depending on the type of logic.

 

By placing an output resistance on the output logic level, this will provide a running "last 32 clock samples" but even when they are all "1" the voltage will never exceed logic (say 5V), and never go below ground. On the other hand given the number of samples which are switched "on", there will be a different output impedance, or current.

 

The next stage is a method to convert this variable output impedance to voltage or I-V: current to voltage. This can be done with an opamp, or discrete design itself. Borbely published a famous jFet I-V design, and then Nelson Pass greatly simplified it into the "Zen I-V" if people want to google, it is a very simple circuit itself.

 

Following the I-V stage is placed an analog filter, often a Sallen-Key lowpass design (which is 2nd order), two of which can be used to get a 4th order low pass filter -- getting rid of the 22Mhz electronic hash. This similarly can be implemented as either an opamp or discrete design and could be either tube or transistor based.

 

So yes this can be entirely chipless comprised of individual transistors or tubes, resistors and capacitors, or can contain logic chips and opamps or any mixture in between.

 

Jabbr,

 

A seminal post !

 

I wish you could come to the DSD 512 May Fest in Munich and spend some time with Jussi and also edbk

 

Best

 

Edward

Sound Test, Monaco

Consultant to Sound Galleries Monaco, and Taiko Audio Holland

e-mail [email protected]

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I wish you could come to the DSD 512 May Fest in Munich and spend some time with Jussi and also edbk

 

Cool-looking gathering.

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One day people will understand that Miska was years ahead of everybody in foreward thinking.

 

*forward* thinking, peeps. Now I understand why this sentence was feeling awkward to me.

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Exactly. Using zynq 7020. sfp/sgmii core -> processor which runs NAA/networkaudiod -> alsa driver -> DSD logic core -> GPIO pins.

 

 

Go jabbr, go!

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Surround: VLC | M-Audio FastTrack Pro | Mac Opt | Panasonic SA-HE100 | Logitech Z623

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Exactly. Using zynq 7020. sfp/sgmii core -> processor which runs NAA/networkaudiod -> alsa driver -> DSD logic core -> GPIO pins.

 

25329964-business-man-with-glowing-exploding-head-concept.jpg

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Have you found Jussi's (Miska) DSC 1 DAC design descriptions here on CA? Discrete DAC should mean DAC chip-less, using only discrete components in an analog low pass filter. No Sabre, TI, etc. DAC chip or FPGA approach. Unless someone is bastardizing the use of the term Discrete DAC. LOL

 

The idea of "no FPGA" is not entirely accurate in this context. An FPGA is never a DAC, as an FPGA always outputs a digital signal. For example, a PS Audio DS or DS-J DAC uses an FPGA to do filtering and oversampling, and then it outputs a DSD 128 stream to a discrete DAC stage, which actually does the conversion to analog, this is still a discrete DAC.

Consider also Chord DACs. They also do oversampling and filtering in an FPGA, but the output from the FPGA then goes to their discrete "Pulse Array" DAC circuit.

These approaches, by using an FPGA to create a high rate data stream, which can then be easily converted to analog by a relatively simple discrete DAC circuit, are really not much different generally to what Miska (Jussi) does: the main difference is that Jussi does the oversampling in a separate computer running HQPlayer, and Chord and PS Audio do the oversampling onboard the component in an FPGA: all of these approaches still do the final conversion from digital to analog via a discrete DAC.

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                                                                                           SONORE computer audio

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The "proper" way to balance the DSC1 circuit is to use 32 additional shift registers for the other side of balanced. One can readily do this using two boards and the existing board outlines and some very simple mods. The DSC1's primary weakness is power supply dependency, as the outputs are directly connected with the power supply via the shift registers. Running balanced registers ameliorates this. There should be enough output to readily just filter this output without other parts. I intend to use a very high quality 1:1 transformer. The parts are on my bench, but sadly I too haven't the time...

Yes the DSC1 is quite good but maybe "clinical" sounding? Certainly great for an initial design with entirely off the shelf parts, and good enough that worth improving.

 

Balancing the DSC1 can be done with a d-flop, perhaps replace I-V with discrete, :

 

 

Zen -> Cen -> Sen, evolution of a minimalistic IV Converter - Page 182 - diyAudio, and discrete JFet SK filters

 

Also upgrade clock, and improve DSD signal isolation from USB input converter.

 

Ultimately provide direct fiber optic Ethernet to DSD output running NAA on embedded ARM with FPGA handling DSD timing from DAC's clocks...

Forrest:

Win10 i9 9900KS/GTX1060 HQPlayer4>Win10 NAA

DSD>Pavel's DSC2.6>Bent Audio TAP>

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