Singxer SDA-6

[R1200CL]

@Miska or anyone else. 

It's not totally clear to me what the clock, internally or externally is doing in a USB to an SPDIF converter. And what frequency is needed. I probably didn’t understand the answers given so far. 
 

Some explanation would be very helpful.

@JohnSwenson  or @Superdad I think you guys know a lot about USB to SPDIF converters, and how they ought to be designed. 
A short explanation from you would be very helpful. I do understand that some sort of isolation between USB and the rest of circuits is good. Is more about how a a good clock (with low phase noise) used in converters, should matter or not.

 

I’m not asking for any technical evaluation of the SU-2. (It’s only on power now. Not connected yet). 

It’s more about understanding the possible (technical) value of adding a better clock.

 

I also think it’s widely accepted that the best solution is to have the DAC do any clocking. But I can’t understand how that could be part of a discussion when I’m only using AES/EBU. 

if this statement is correct “The AES/EBU and S/PDIF formats both have word clock in the digital audio stream”, then it seems to me the quality of the clock may matter. 
I was trying to read “GUIDELINES THE EBU/AES DIGITAL AUDIO INTERFACE” there they talk about clock recovery. But I don’t understand if that matters or not as the DAC has its own clock. (I assume). 
 

 

[Miska]

7 minutes ago, R1200CL said:

@Miska or anyone else. 

It's not totally clear to me what the clock, internally or externally is doing in a USB to an SPDIF converter. And what frequency is needed. I probably didn’t understand the answers given so far. 

 

Typically for 44.1k-base rate family you would need a 22.5792 MHz or 45.1584 MHz clock. And for 48k-base rate familiy 24.576 MHz or 49.152 MHz clock. You can find plenty of clock oscillators for these frequencies from manufacturers like Crystek or NDK. These are 512 or 1024 multiples of the base sample rate.

 

I2S data clocked using these clocks between the USB interface and the S/PDIF transmitter contains two clocks. Word aka left/right clock which toggles at the sampling rate. And bit clock which is 32x the sampling rate. For in case of 192 kHz data it is 6.144 MHz.

 

At 192 kHz sampling rate, the signal on S/PDIF is toggling at 24.576 MHz rate.

 

When you switch between the two sampling rate families, you need to switch between two separate master clocks.

 

25 minutes ago, R1200CL said:

I also think it’s widely accepted that the best solution is to have the DAC do any clocking. But I can’t understand how that could be part of a discussion when I’m only using AES/EBU.

 

Yes, that's the case. But when using S/PDIF or AES/EBU, typically you don't have a DAC side clocking other than a clock recovered using PLL from the S/PDIF or AES/EBU signal.

 

26 minutes ago, R1200CL said:

I was trying to read “GUIDELINES THE EBU/AES DIGITAL AUDIO INTERFACE” there they talk about clock recovery. But I don’t understand if that matters or not as the DAC has its own clock.

 

There are some special solutions where DAC has it's own clock when using S/PDIF or AES/EBU input, but this is a relatively rare case and it needs complex implementation because you have two separate clocks that are running independently at their own frequencies. So most of the time this is not the case.

 

[R1200CL]

Thanks Miska.
 

My understanding of this answer is that it’s totally meaningless to have a 10 MHz clock in a USB to SPDIF converter. (General speaking). 

http://www.singxer.com/pd.jsp?id=80 (Auto translate using chrome). 
 

On the other hand, it may seems that the 10 MHz input is used to convert up to the needed frequencies in a converter, and then maybe the quality of external clock matter. Maybe Singxer has done something very clever. 
 

To reframe the question, does the quality if the 44.1k-base rate family 22.5792 MHz or 45.1584 MHz clock and the 48k-base rate familiy 24.576 MHz or 49.152 MHz clock matter ?

 

44 minutes ago, Miska said:

But when using S/PDIF or AES/EBU, typically you don't have a DAC side clocking other than a clock recovered using PLL from the S/PDIF or AES/EBU signal.

 So one could assume better input to this PLL, may affect further what’s happening in a DAC ?

 

[R1200CL]

20 hours ago, Miska said:

Yes, if you have a better clock at the source (USB to S/PDIF converter), then the PLL at receiver side has better chances or recovering a clean clock from the S/PDIF signal.

Aha.  Very good 😀

Sorry for not getting this point before.

 

This qualifies for testing using a better external clock. 
 

Thanks Miska

[R1200CL]

Product introduction:

 

SU-2 digital interface is a new high-performance USB digital audio interface developed by our team. It adopts a microprocessor with the latest ARM Cortex-M4 as the main control of the USB data part. SU-2 adopts the self-developed ultra-low jitter clock system (ACCUSILICON's AS-318B series, ultra-low jitter up to the femtosecond level), and the large-capacity FPGA as the processing core of Digital audio data, with standard USB2.0 input. Interface, rich output interface, including XLR balanced output AES, coaxial RCA and BNC, I2S interface with HDMI socket output, perfect main clock and word clock (WCLK) output. SU-2 supports external 10Mhz clock input and adopts the common 50 ohm input impedance design.

SU-2 is not only a USB interface, but also can be used as a stand-alone main clock product.

1. When used as a stand-alone master clock, you can output 44.1K-384K word clocks, or 22.5792Mhz-49.152Mhz master clock. ( When not connected to USB, it will be used as the main clock device by default)

2. It can also be used as a frequency converter when using an external 10Mhz clock input; it supports 10Mhz conversion to 44.1K-384K word clock, or output 22.5792Mhz-49.152Mhz master clock.
 

 

SU-2 is the new architecture USB interface we have developed to replace the original SU-1; PCM sampling rate up to PCM 768K and DSD up to DSD1024. Using large-scale FPGA as the core of operation processing, we decentralize some of the FPGA algorithm technology of the flagship interface SU-6 to SU-2; it is positioned in the middle and high-end interface, mainly using the following three unique technologies:

1. Full isolation technology (ground isolation), using 150Mbps full isolation chip, can completely isolate interference from PCs;

2. Source synchronization technology and FPGA shaping technology reshape the isolated I2S signal; thus eliminating the additive jitter brought by the isolation chip;

3. The independently developed clock system adopts ACCUSILICON's high-performance crystal oscillation, low phase noise and low jitter. You can also choose an external 10Mhz clock to support various atomic clocks, constant temperature crystal oscillation, and GPDSO input.

 

• Technical indicators:

  The sampling rate supported by each output interface:

  PCM: 44.1KHz, 48KHz, 88.2KHz, 96KHz,

  176.4KHz, 192KHz, 352.8KHz, 384KHz, 705.6KHz, 768KHz

  [of which I2S out supports total sampling rate, S/PDIF supports up to 384KHz, DOP128]

• 2.8 MHz (DSD64) - DOP, native

• 5.6 MHz (DSD128) - DOP, native

  11.2 MHz (DSD256) - DOP, native

  22.5792 MHz (DSD512) - DOP,Native

  45.1584 MHz (DSD1024) - native

  [where I2S out supports all DSD formats, S/PDIF and AES/EBU support DSD128 DOP mode]

  Bit width: up to 32 bits over I2S output

  Up to 24 bits over S/PDIF

 

• Electrical standards for each interface:

  1. The USB input socket is a standard USB-B-type parent seat, and the USB power supply range is 4.5V-5.1V;

  2. The RCA interface outputs the standard S/PDIF signal, with a level of 550mV (connected to the standard load) and the output impedance of 75 ohms;

  3. The power input is 115V/230V AC, and the internal power supply is powered by TALEMA imported transformer.

Design details:

1. Implement the design concept of electricity as the mother of sound, attach importance to the design of power circuits, and adopt high-performance, low-noise and fast-response LDO as the main power supply. The whole board adopts multiple independent LDO power supply, and the clock part even adopts ADI's ultra-low noise LDO, laying a solid foundation for ensuring the ultimate output performance.

2. The PCB motherboard adopts a 4-layer circuit board design to ensure that it has a complete ground level and power layer, and adopts a high-speed digital design method to ensure the signal integrity and power supply integrity of the whole board. Special processing of clock signals adopts inclusive design and accurate impedance control, thus ensuring the signal quality of the clock and improving its anti-interference ability. The input and output signals follow the standard design, especially the USB high-speed signal adopts 90 ohm differential impedance control.

 

System compatibility:

1, Windows 7, Windows 8, Windows 10; 32/64 bit, requires a dedicated driver

2, Native MacOS 10.6 and later, using the system's own driver

3, Native Linux with UAC2 compliant kernel, using the system's own driver, (tested on Ubuntu and Daphile systems, based on the INTEL X86 platform)

4. Android OS 4.2 and above require devices to support OTG functions. Generally speaking, Android 9.0 and above systems are supported by default, and it is recommended to use below 9.0 with special players.

 

The I2S interface adopts HDMI socket output:

1. LVDS differential signal with a level of 3.3V;

2. DSD ON signal, 5V power supply (small current), MUTE signal internal CPLD has been processed, and there will be no need to output MUTE signal;

3. The DSD ON signal can be defined by itself. The DSD ON signal can be output arbitrarily to the pins of the socket's PIN 13, 14, 15, 16.

 

 

[Miska]

3 hours ago, R1200CL said:

To reframe the question, does the quality if the 44.1k-base rate family 22.5792 MHz or 45.1584 MHz clock and the 48k-base rate familiy 24.576 MHz or 49.152 MHz clock matter ?

 

Yes, that's why I use for example Crystek CCHD-957 oscillators in my DAC prototypes. These are available at those frequencies. The effect is more definite when it is directly clocking the conversion stage inside a DAC. Also SDA-6 Pro model comes with those same oscillators.

 

3 hours ago, R1200CL said:

So one could assume better input to this PLL, may affect further what’s happening in a DAC ?

 

Yes, it makes life easier for the PLL. It doesn't translate directly into actual conversion clock performance, but it helps.

 

[R1200CL]

I think I’m getting closer to some understanding.

The clocks in SU-2 doesn’t look bad either I guess. 
http://www.accusilicon.com/docs/AS318BM.pdf 

2 different versions in use. I suppose in order to each facilitate 44.1 and 48 base rate families. 
 

From SDA-6 specifications:

“The standard version of the crystal oscillation is AS-318B, and the high-configuration version is CCHD-957.” (Edit. As stated by @Miska)

 

Obviously is CCHD-957 is a better option and not offered for the SU-2.
OK, that may be a possible future DIY upgrade 😀 (Not even Kitsune has that on the list). 
 

So then there is some FPGA that takes the correct multiple from the clocks based on type of audio resolution is feed to the converter (or DAC). 
 

And an external 10 MHz is bypassing the internal clock, and somehow is able to be create same needed frequencies.

That’s the part of something that’s a very mysterious thing.
 

How a single 10 MHz can replace the function of those two internal clocks ?
Maybe there still is a chance I haven’t understood how this 10 MHz external input actual is working and it’s real mission. 

 

The external 10 MHz clock input on SDA-6 is described as this:

“SDA-6 supports external clock input, of which USB supports 10M clock input, and other interfaces support WCK input.“ 

So if it’s 10 MHz only USB, then shouldn’t that be same for the SU-2 ? There must something very fundamental I’m missing.

 

Maybe this will also be covered by @JohnSwenson clock paper too ?

In what application is a 10 MHz good to use and why ?

When do we use a Word clock ? (WCL)

Will circuits that produce multiple frequencies degrade output from the clock. 

[Miska]

1 hour ago, R1200CL said:

How a single 10 MHz can replace the function of those two internal clocks ?
Maybe there still is a chance I haven’t understood how this 10 MHz external input actual is working and it’s real mission. 

 

Through a programmable fractional PLL. A bit like a sample rate converter that can convert between rate families. This is also similar to audio clock generation on HDMI interface where audio clocks are generated from the video pixel clock.

 

1 hour ago, R1200CL said:

When do we use a Word clock ? (WCL)

 

It is mostly used by studios when you need to synchronize multiple DACs or ADCs running in parallel. Since it usually runs at 44.1 kHz, it is also prone to a lot of jitter.

 

1 hour ago, R1200CL said:

Will circuits that produce multiple frequencies degrade output from the clock.

 

You mean the ones that create multiple frequencies from single reference? Yes, usually they do.

 

[R1200CL]

23 minutes ago, Miska said:

Through a programmable fractional PLL. A bit like a sample rate converter that can convert between rate families.

OK. That’s the secret 😀

Then maybe a very good 10 MHz clock can replace the dual internal ones.
Both SU-2 and the SDA-6. So worth testing 😀

 

Just why wouldn’t designers then use programmable fractional PLL and a 10 MHz clock in general instead of dual clocks of different frequencies ?

Not remember what was said before in this tread about those two available SDA-6 options, one may benefit of purchasing the standard one, and use the “saved” money on a good external clock. 
 

I guess only listen will tell.

So first step for me is to compare SU-1 to SU-1 during next days. Then test with external clock.

 

Thanks for clarification again Miska. 

[JohnSwenson]

1 hour ago, R1200CL said:

I think I’m getting closer to some understanding.

The clocks in SU-2 doesn’t look bad either I guess. 
http://www.accusilicon.com/docs/AS318BM.pdf 

2 different versions in use. I suppose in order to each facilitate 44.1 and 48 base rate families. 
 

From SDA-6 specifications:

“The standard version of the crystal oscillation is AS-318B, and the high-configuration version is CCHD-957.” (Edit. As stated by @Miska)

 

Obviously is CCHD-957 is a better option and not offered for the SU-2.
OK, that may be a possible future DIY upgrade 😀 (Not even Kitsune has that on the list). 
 

So then there is some FPGA that takes the correct multiple from the clocks based on type of audio resolution is feed to the converter (or DAC). 
 

And an external 10 MHz is bypassing the internal clock, and somehow is able to be create same needed frequencies.

That’s the part of something that’s a very mysterious thing.
 

How a single 10 MHz can replace the function of those two internal clocks ?
Maybe there still is a chance I haven’t understood how this 10 MHz external input actual is working and it’s real mission. 

 

The external 10 MHz clock input on SDA-6 is described as this:

“SDA-6 supports external clock input, of which USB supports 10M clock input, and other interfaces support WCK input.“ 

So if it’s 10 MHz only USB, then shouldn’t that be same for the SU-2 ? There must something very fundamental I’m missing.

 

Maybe this will also be covered by @JohnSwenson clock paper too ?

In what application is a 10 MHz good to use and why ?

When do we use a Word clock ? (WCL)

Will circuits that produce multiple frequencies degrade output from the clock. 

Almost nothing in audio uses 10MHz directly, thus a 10MHz input is used as a reference to a clock synthesizer chip. These are PLL circuits with simple to complex divider circuits which allow them to output an extremely broad range of frequencies with very fine gradations.

 

As with anything there are cheap crap, pretty good and very good versions of these. Do they degrade the reference? As with everything, that depends. Some are designed to be "jitter attenuating", if you feed these a lousy clock they will improve it. These are good for things like cleaning up a recovered clock from SPDIF. The other type is designed to take a really good reference and degrade it as little as possible. The best of these only have a very small degradation in the closer in phase noise.

 

So if you use a10MHz  reference feeding the best synthesizers outputting say 49.xxx, an oscillator of the same series directly outputting 49.xxx will be slightly better, but not by much. BUT if that 10MHz reference is significantly better, then the output of the synthesizer will be significantly better at low offsets than the direct oscillator. The higher offsets (say above 4KHz) will be worse, but the low offsets seem to matter much more than the high offsets.

 

There is another effect here. For a given oscillator circuit, crystal quality etc, lower frequency crystals tend to have slightly lower phase noise (when compensated by the 6dB per octave rule) than higher frequency versions. Thus you might actually get slightly lower phase noise with a 10MHz oscillator feeding a really good synthesizer than with the same series oscillator outputting that frequency.

 

Using the various options a designer can tweak things to get the best performance for the cost. Using a single better oscillator feeding a good synthesizer my very well give better performance than two somewhat worse oscillators.

 

There are downsides, the good synthesizer chips take two or three supply voltages , which increase supply complexity and cost.

 

In my designs I did a bunch of analysis and decided that the single very good oscillator feeding a very good synthesizer was the best way to go. Different designs are going to come with different optimizations.

 

John S.

[Miska]

6 hours ago, R1200CL said:

Then maybe a very good 10 MHz clock can replace the dual internal ones.

 

Sure it can replace, but I personally don't see a point in added complexity where result is likely quite a bit worse.

 

6 hours ago, R1200CL said:

Just why wouldn’t designers then use programmable fractional PLL and a 10 MHz clock in general instead of dual clocks of different frequencies ?

 

Because it is more complex, more expensive and produces inferior results.

 

It is best to have a good oscillator (like the Crystek) at the frequency you need, at the place you need. That's why you'd usually find two of such Crystek's inside a DAC, next to conversion section. The unused ones are disabled through the corresponding enable/disable pin.

 

[fmzip]

17 hours ago, R1200CL said:

I think I’m getting closer to some understanding.

The clocks in SU-2 doesn’t look bad either I guess. 
http://www.accusilicon.com/docs/AS318BM.pdf 

2 different versions in use. I suppose in order to each facilitate 44.1 and 48 base rate families. 
 

From SDA-6 specifications:

“The standard version of the crystal oscillation is AS-318B, and the high-configuration version is CCHD-957.” (Edit. As stated by @Miska)

 

Obviously is CCHD-957 is a better option and not offered for the SU-2.
OK, that may be a possible future DIY upgrade 😀 (Not even Kitsune has that on the list). 

 

I had tried an Accusilicon AS-318B in my LKS DAC MH-DA004 which I heavily modded. I then swapped it out for a Crystek CH950X and the sound was just so much better. This lead me to do the exact same swap to with my Kitsune SU-2, swapped out the Accusilicon clocks for Crystek. The Kitsune SU-2 is so much better than the Sonore UltraDigital it had replaced (using i2s to feed my DAC)

 

I had started following this thread thinking that I needed to try something other than an ESS DAC. I am at the point right now that my modding days are over. My system sounds so good, I really am lost for words. The days of the glare of the ESS DAC's signature are gone. I'd highly suggest the Kitsune SU-2/MH-DA004 with mods to anyone.

 

Quote

 

 

[fmzip]

If you want to do the mod, I used the RHEA Adapter board from Twisted Pair Audio, scroll all the way to the bottom of this link:

 

Rhea Adapter Board

 

And also some really good soldering skills. I work at a company that does printed circuit board assembly so I had one of the solderers do the surgery under a microscope, soldering the surface mount Crystals to the RHEA Adapter board

[R1200CL]

1 hour ago, fmzip said:

If you want to do the mod, I used the RHEA Adapter board from Twisted Pair Audio, scroll all the way to the bottom of this link:

This one:

 

So the clocks not exchangeable on the PCB. Holes doesn’t fit ?

 

Or is there an option to purchase the correct boards including the right versions of the Crystek CCHD-957

 

 

Did you actually notice a difference ?

 

What regulators did you add ?

Any other tweak ?

 

[fmzip]

39 minutes ago, R1200CL said:

This one:

 

So the clocks not exchangeable on the PCB. Holes doesn’t fit ?

 

Or is there an option to purchase the correct boards including the right versions of the Crystek CCHD-957

 

 

Did you actually notice a difference ?

 

What regulators did you add ?

Any other tweak ?

 

The regulators you see were installed as part of the Kitsune edition mod. The only mod I did to the unit was the crystal swap. And yes, I notice a difference. The Accusilicon part is a Thru-hole Crystal meaning the pins go thru the board and get soldered. The Crystek is a surface mount part, it has no leads which is why it need to be soldered to the adapter board which has 4 leads, just like the Accusilicon part. You need two of these little adapter boards to mount the Crysteks, the far right bottom image will give you an idea of what you are working with. Disregard everything else in the image, it was just for reference to show the green Rhea Adapter board and the Crystek Crystal. Scroll all the way to the bottom of the Twisted  Pair link I provided, they are $8.50 each. And correct, without using the adapter board, you cannot use the Crystek

 

 

 

[R1200CL]

 

Just ordered. Now must find the clocks. 

[fmzip]

1 minute ago, R1200CL said:

Correct! Scroll up...edited my post to show you a pic

[etane]

Singxer SU2 is an indispensable upgrade to my D90 MQA.  That is all.

[fmzip]

41 minutes ago, etane said:

Singxer SU2 is an indispensable upgrade to my D90 MQA.  That is all.

 

I agree. There's not much talk of the SU-2. I really lucked out with my Kitsune SU-2, found it used for $350. Upsampling to DSD512 with HQPlayer/Roon never sounded so good :)

[etane]

1 minute ago, fmzip said:

 

I agree. There's not much talk of the SU-2. I really lucked out with my Kitsune SU-2, found it used for $350 :)

I think I saw the ad but wasn't sure about whether I actually wanted it at the time.  Now I do wonder about the improvements but not curious enough to spend marginal time and money.  Perfectly happy with my system, first time since forever.

[fmzip]

7 minutes ago, etane said:

I think I saw the ad but wasn't sure about whether I actually wanted it at the time.  Now I do wonder about the improvements but not curious enough to spend marginal time and money.  Perfectly happy with my system, first time since forever.

I agree with you. It becomes diminishing returns.

 

I like your comments "since forever" and I couldn't agree more. I can't remember the last time I've spent so much time listening to music. The LKS/Singxer combo is bliss for me

[Superdad]

3 hours ago, fmzip said:

 

Thanks for posting this full view of the Singxer SU-1 board.  What puzzles us about it is:

 

a) There are 2 sets of 45.xxx/49.xxx MHz clocks on the board--the Crystek (or Accusilicon as stock) and below those a small cheap pair (now visible in the photos as also being 45.xxx/49.xxx. It is not clear what the second set is for.

 

b) While there is a 10MHz external clock input, there is no sign of a clock synthesizer on the board. There absolutely must be some type of PLL synthesizer present to reference from the 10MHz and produce 45.xxx/49.xxx clock lines. While it is possible they are using the PLLs in the Spartan-6 FPGA as the clock synth, the performance from that would be quite bad (and thus one would be much better off sticking with the main on-board clocks rather than using an external 10MHz reference). 

I suppose a clock synth could be on the bottom of the board, but would need to see pics of the underside to know.

[R1200CL]

11 hours ago, Superdad said:

I suppose a clock synth could be on the bottom of the board, but would need to see pics of the underside to know.

Here you go. 
I think you just saved me an external clock for this one. However question then remains what that external 10 MHz actually does. Or how. Well you already said Spartan 6.....

 

 

 

[fmzip]

17 hours ago, Superdad said:

 

Thanks for posting this full view of the Singxer SU-1 board.  What puzzles us about it is:

 

a) There are 2 sets of 45.xxx/49.xxx MHz clocks on the board--the Crystek (or Accusilicon as stock) and below those a small cheap pair (now visible in the photos as also being 45.xxx/49.xxx. It is not clear what the second set is for.

 

b) While there is a 10MHz external clock input, there is no sign of a clock synthesizer on the board. There absolutely must be some type of PLL synthesizer present to reference from the 10MHz and produce 45.xxx/49.xxx clock lines. While it is possible they are using the PLLs in the Spartan-6 FPGA as the clock synth, the performance from that would be quite bad (and thus one would be much better off sticking with the main on-board clocks rather than using an external 10MHz reference). 

I suppose a clock synth could be on the bottom of the board, but would need to see pics of the underside to know.

Hi Alex, you and I spoke on the phone a few months back, I am the guy in CT that works at a contract manufacturer. I do not know how any of this stuff actually works, but I do know how it's manufactured ;)

 

The photo is of a Kitsune SU-2. A gentleman on headfi named b0bb who is the resident expert engineer on modding referred to the other two as "slave clocks". He had asked me if I could look into seeing who the manufacturer of the parts were as the markings came up with an empty search. My engineering deciphered the parts for him as:

 

They are made by Taitien. Digikey carries them. They come in two different sizes. One is the OY series and one is the OX series.

The part numbers are OYEUDCJANF-45.158400 or OXEUDCJANF-45.158400 and OYEUDLJANF-49.152000 or OXEUDLJANF-49.152000,
depending on the size you need.

 

b0bb's reply was:

 

Thanks.

Taitien has a partnumber decoder on their website, the partnumber of the XOs are VTEMACJ-xxx

This is consistent with the TEMACJ designation on the case.

7mm x 5mm footprint size, 6 connection pads, 3.3V, CMOS output
This is the VT-M part: https://www.taitien.com/wp-content/uploads/2016/01/XO-0052-VT-MCMOS-Type.pdf

Voltage controlled XO, the control voltage is derived from the difference in the reference frequency and the current output frequency of the slave
Reference is either from the onboard SU2 reference crystals or the 10MHz external reference.

Performance is average, close in phasenoise is about 5.6x (15dB) worse @100Hz compared to the CCHD957 for a 50Mhz operating frequency
(-85dBc/Hz vs -100 dBc/Hz)
 

[SwissBear]

21 hours ago, Superdad said:

 

Thanks for posting this full view of the Singxer SU-1 board.  What puzzles us about it is:

 

a) There are 2 sets of 45.xxx/49.xxx MHz clocks on the board--the Crystek (or Accusilicon as stock) and below those a small cheap pair (now visible in the photos as also being 45.xxx/49.xxx. It is not clear what the second set is for.

 

b) While there is a 10MHz external clock input, there is no sign of a clock synthesizer on the board. There absolutely must be some type of PLL synthesizer present to reference from the 10MHz and produce 45.xxx/49.xxx clock lines. While it is possible they are using the PLLs in the Spartan-6 FPGA as the clock synth, the performance from that would be quite bad (and thus one would be much better off sticking with the main on-board clocks rather than using an external 10MHz reference). 

I suppose a clock synth could be on the bottom of the board, but would need to see pics of the underside to know.

 

Hi Alex,

 

Thanks for sharing your investigations and suppositions.

What I always find more interesting than suppositions, is measurements and listening experience.

 

In this post: 

I shared measurements made  by l7audiolab which clearly show that even a middle class 10 MHz clock (Gustard C-18) had a positive effect on the measurement of jitter at the output of a DAC which was driven by a SU-2.

 

I have had an SU-2 in my setup for some time now, driven by a Mutec REF-10, and I can assure you that this 10 MHz clock leads to better results than the oscillators of the SU-2 alone.

 

Both measurements and listening experience show that the implementation made by Singxer of the 10 MHz clock input is performing well, whatever clever suppositions tend to infer.

 

Just y 2c.

 

[EDIT] Having written that, I also noticed that the impact of an external clock was more important when the clock is directly connected to the SDA-6 than when the clock is connected to the SU-2. Which could lead to the hypothesis that the implementation of the external clock signal is better in the SDA-6 than in the SU-2.