Debate of DAC design regarding DSD vs PCM among 5 VIPs

[Daudio]

2 minutes ago, mmerrill99 said:

I can't see how this integration can explain a reduction in amplitude to the extent that we see in the FFT plot here

 

Could it be that that FFT is representing the density of phase errors ? Such that they are most dense close to the target frequency (smaller deviations). and less dense as the error increasingly deviates from the norm, but occurring less often, thus the shape of the envelope. All of this occurring outside of any consideration of the consistent amplitude of the signal that contains clock jitter.

 

Sorry to interrupt this interesting dialogue, but that just popped into my head as I was reading, so what the hell...

 

[mmerrill99]

deleted

[mmerrill99]

12 minutes ago, Daudio said:

 

Could it be that that FFT is representing the density of phase errors ? Such that they are most dense close to the target frequency (smaller deviations). and less dense as the error increasingly deviates from the norm, but occurring less often, thus the shape of the envelope. All of this occurring outside of any consideration of the consistent amplitude of the signal that contains clock jitter.

 

Sorry to interrupt this interesting dialogue, but that just popped into my head as I was reading, so what the hell...

 

Yes, that's my thinking on it & what I'm trying to convey

As I said I look on that  FFT plot as a statistical representation of the phase errors - close in their occurrence is high, further out their occurrence is low

 

What I was trying to point up is what I often see as a misinterpretation of this type of plot, interpreting the low dB scale as representative of the actual amplitude of the error signals 

 

As I was saying - FFTs are like long exposure photographs - in this sort of photo a stationary car's headlights will be far brighter than a moving car's headlights - in real world they will both be equal brightness

[Daudio]

1 minute ago, mmerrill99 said:

FFTs are like long exposure photographs - in this sort of photo a stationary car's headlights will be far brighter than a moving car's headlights - in real world they will both be equal brightness

 

Or, another example for this purpose could be an extended exposure of the area around a subway entrance/exit on a busy city square. The distribution of people might look random in a single exposure, but over time the entrance will be the locus of people density, decreasing with distance.

 

I just love videos at different time scales. Like watching days cycle by in seconds, or glaciers retreating, or starfish attacking prey.

There is a name for that multiple-timed-exposure photographic technique, but I just can't remember it now 

[jabbr]

3 hours ago, mmerrill99 said:

... I can't see how this integration can explain a reduction in amplitude to the extent that we see in the FFT plot here - maybe I'm being stupid? 

No, I'm not sure that the goal has been to represent amplitude per se. An FTT does have an amplitude component, but we have been focusing on phase. Assuming amplitude is constant with time, the idea of "bins" being filled is a way to look at it (hesitating only because I haven't entirely thought this through...)

 

What do you mean by "reduction in amplitude"? I very well might be assuming the wrong thing.

[mmerrill99]

11 hours ago, jabbr said:

No, I'm not sure that the goal has been to represent amplitude per se. An FTT does have an amplitude component, but we have been focusing on phase. Assuming amplitude is constant with time, the idea of "bins" being filled is a way to look at it (hesitating only because I haven't entirely thought this through...)

 

What do you mean by "reduction in amplitude"? I very well might be assuming the wrong thing.

What I mean is that we look at a spike on an FFT  & read off the amplitude of that signal from the dBs on the Y-axis - so a signal is -3dB , -6dB, -90dB down from 0dB - this gives us the amplitude of the signal & would match an SPL reading taken in-room.

 

Other parts of an FFT, like the 'grass' at the bottom from which the spikes protrude, are often mistakenly read as the 'SPLlevel' of the "noise floor". As we know this is incorrect & to get the true noise floor level we need to calculate the process gain of the FFT & add this to the plotted level of the 'grass'

 

My point is that the skirt we see around the base of a signal spike, which in this case is dues to jitter from phase noise, is also not to be read directly off the FFT plot as-is but needs some different interpretation & I haven't seen anyone address this before to come up with the way to interpret signal skirts in an FFT.

 

I think the natural instinct is to view these skirts as down at -160dB -150dB, rising to meet the signal spike at  some dB level. What is the correct interpretation of this skirt? This isn't easy to discuss as most jitter FFTs use a x-axis HX scale which is too wide a range to see the detail of what's in close to the 11KHz jitter signal. The reason for this wide range is that they are examining the overlaid frequencies in the jitter test signal usually seen as spikes further away from the 11KHz main signal.

 

Here's something that illustrates - the first plot is two overlaid FFTs  (one black, one  red) of a jitter test signal - the black one is the result of using a clock with lower close-in phase compared to the red one. So looking at this plot, not much difference between them, right?

The x-axis in this case is the Hz offset from the signal spike.

 

So when the blue box is zoomed into, we see a difference which wasn't evident before

 

In this graph the x-axis is a much finer division - we are seeing 100Hz either side of the signal spike. From about 40Hz out we see the rise of the red skirt & it meets the signal spike up around -90dB (this is probably about 2Hz away from the signal?). Now if we zoomed in closer we could see the differences closer to the test signal - maybe in at 0.1Hz away from the spike - we would probably see it merging with the spike very much higher on the y-axis maybe higher than -20dB just based on eyeballing that slope.

 

That's one point about why Miska's FFT plot initially shown & annotated as "less bad 'good' jitter" may not be fully accurate.

 

My other point is that I find it less than intuitive trying to interpret what this skirt actually signifies. Looking at the zoomed in FFT plot above, to me, it doesn't signify that the error signal 20Hz away from the main signal is down @ -120dB & therefore of little concern to perception. This is my main focus - what is the perceptual effect of such error signals? Maybe I'm wrong in my thinking.

 

Allow me to talk through this & maybe at the end of this I'll have changed my thinking?

 

To my mind an FFT plots the energy in the bins into which the full signal is divided. So for a a narrow band signal which falls in few bins, the energy plotted is close to the actual SPL that would be measured on playback & therefore has perceptual significance. But for wideband signal such as noise, it's power does not fall into a small number of bins, it is spread across a wide number of bins. So, in this case, the FFT is showing the energy in each of the bins across the full frequency spectrum anlayzed. This will necessarily be plotted lower than the actual SPL which would be measured in room, on playback - so perceptually the effect will be greater than what is read as the dB level read directly from y-axis. We know how to compensate for this discrepancy - by calculating the FFT process gain & adding this to the y-axis level readout.

 

Now what way to treat FFT plots of signals which aren't narrow band & not full spectrum wide-band but wideish-band? How to translate from FFT dB level to actual dB level for these signals? In other words how can we correct it to better represent it's perceptual effect (just talking about amplitude here)

 

Let's not forget that FFTs are just a signal analysis which are at times useful to represent aspects of the signal but can also mislead & confuse in other areas aspects. They are NOT the signal itself & therefore we have to be careful of how to interpret the plots.

[jabbr]

3 hours ago, mmerrill99 said:

...

The x-axis in this case is the Hz offset from the signal spike.

 

So when the blue box is zoomed into, we see a difference which wasn't evident before

 

In this graph the x-axis is a much finer division - we are seeing 100Hz either side of the signal spike.

 

...

 

Yes.

Clearly need to look at a more narrow band distribution. I've used the term "linewidth" to describe this (from laser literature). I haven't considered the details of how these effects might affect SPL. I've been concerned with how to take fine grained close-in measurements in various parts of the DAC circuit.

[louisxiawei]

Interview with Robert Watts from Chord

 

5.1 Many people think by using the way of interpolation to do the up-sampling will damage the original signal, but the Chord always uses very high up-sampling rate, what is the intention by doing this?

 

In the part of analogue playback, having the original signal as much as possible is surely correct, but it will be wrong if following the same rules in the digital processing domain. After the original analogue signal is converted to digital ones during recording, the analogue signal converted from digital signals surely differs from the original analogue signal. In other words, during D-A conversion process, what we want is not the original digital signal but to “rebuild” the original analogue signal.

 

In order to achieve this, only by using digital filters and up-sampling approaches to fix the lost information of digital signal. Then we can try to get the analogue signal much closer to the original ones. That’s why we up-sample files by 2048 times.

 

 

5.2 What's the advantage of high-rate up-sampling?

 

One credit of high-rate up-sampling is that it can significantly reduce the negative impact of the jitter. The jitter causes the distortion of background noise modulation, which fluctuates with the music signal. This kind of distortion is even worse than harmonic distortion, consequently result in a ear-piercing and rigid sounding in practice. By upsampling at high rate to reduce this distortion marginally, the infamous so-called “digital sounding” is no longer present.

 

 

All Rob's interview has been translated. Sorry for the late update, I'm quite busy this week.

[louisxiawei]

Interview with Ted Smith from PS audio

 

4.2 Does it mean that the chips of some Delta sigma DAC are not 1 bit?

Although most of the dac chip on the market belong to Delta Sigma modulation category, however they are multi-bit DACs, this kind of DAC chip does not have the merit of 1 bit DSD. You may ask why most of these DSD chips are multi-bit? That is because true 1-bit DAC is very demanding in terms of power supply quality, jitter and noise control. Those factory-made dac chips make analogue and digital circuits all integrated into one piece of chip, which not only result in high noise but also being difficult to fulfill the demand for high-quality components and power supply. Hence, these DSD chips then have to use 4 bits to do the noise shaping to reduce the noise so as to lower the requirement for filtering circuit. That’s why I give up those dac chips and insist on building my own discrete 1-bit DSD DAC and use FPGA to do DSP and upsampling conversion.

 

Our Directstream DAC uses Xilinx Sparatan 6 FPGA as DSP algorithm engine, its processing power outperforms these dac chips plus our discrete DSD circuit that can separate digital circuit from analogue one. Thanks to the discrete design, we don’t even need to worry about the issue of heat dissipation of the heavy-load algorithm and the noise can be significantly reduced. With the help of regulated power supply circuit and passing through multiple filtering, the 1 bit DSD dac then can be considered to be ideal.

[Solstice380]

@louisxiawei.  I want to thank you again for work in translation.  A very nice gift to the CA community!

[mansr]

11 hours ago, louisxiawei said:

Interview with Ted Smith from PS audio

 

4.2 Does it mean that the chips of some Delta sigma DAC are not 1 bit?

Although most of the dac chip on the market belong to Delta Sigma modulation category, however they are multi-bit DACs, this kind of DAC chip does not have the merit of 1 bit DSD. You may ask why most of these DSD chips are multi-bit? That is because true 1-bit DAC is very demanding in terms of power supply quality, jitter and noise control. Those factory-made dac chips make analogue and digital circuits all integrated into one piece of chip, which not only result in high noise but also being difficult to fulfill the demand for high-quality components and power supply. Hence, these DSD chips then have to use 4 bits to do the noise shaping to reduce the noise so as to lower the requirement for filtering circuit. That’s why I give up those dac chips and insist on building my own discrete 1-bit DSD DAC and use FPGA to do DSP and upsampling conversion.

This makes very little sense, if any. Multi-bit sigma-delta modulators are used to improve the noise shaping performance. It has nothing to do with electrical noise in the chip. These aspects are simply not related whatsoever. This statement reads like Mr Smith is making up plausible-sounding excuses in defence of a design approach he favours. I'm not saying his designs aren't good, perhaps even better than many single-chip solutions, but the reasoning above is still bogus.

[louisxiawei]

21 minutes ago, Solstice380 said:

@louisxiawei.  I want to thank you again for work in translation.  A very nice gift to the CA community!

My pleasure. I think the knowledgeable reply from experts regarding these interview is the real gift for all of us. 

[louisxiawei]

Interview with Ted Smith from PS audio

 

4.4 Are PCM signal being upsampled 10 times before D-A conversion?

 

Yes, that’s correct. No matter PCM or DSD signal, once they reach our DirectStream DAC, signal will pass through my developed FPGA to do the DSP, upsampling all signal at the same sampling rate. As a result, DirectStream DAC only needs one single base clock, sending out constant clock frequency so as to unify the clock during DSP. This can not only reduce the jitter significantly but also can remove the PLL that can easily produce jitter. DSD dac is very sensitive to the jitter, therefore reducing the jitter is very important. Furthermore, after eliminating the high-frequency noise by upsampling by 10 times, the low pass filter can also be considerable simplified, only need to have a filter circuit at a gentle slope.

[louisxiawei]

Interview with Ted Smith from PS audio

4.5 It's quite difficult to do the DSD signal processing. However, DirectStream DAC uses digital volume control, can you explain how it works?

 

The 10 times up-sampling mentioned before actually is a conversion of PCM where the digital volume control is also carried during this process. When music signal is upsampled by 10 times to the resolution of DSD at 30-bit depth, carrying a 20-bit digital volume control can not only set up a lossless digital volume control, but also result in a much lower distortion compared to any other analogue or digital volume control, which is good enough to replace the pre-amplifier in the system to achieve a very simple setup by connecting DAC directly to power amplifier.

[louisxiawei]

Interview with Florian Cossy from CH Precision

 

3.1 Why does C1 use muti-bit R2R modulation instead of normal Delta-sigma?

From the test result we have done in our research lab, the data of Delta-sigma modulation is more perfect than R2R. However, this perfect result is derived from a single constant test signal, the frequency response and amplitude of the real music changes all the time. When the music signal is being played back, Delta-sigma will cause error result in distortion, the problem of high-frequency noise of 1 bit DSD dac is much worse than mutli-bit Delta sigma DAC chip. Thus, R2R is a more accurate and appropriate approach for “real music” playback instead of signal test. This is why we pick R2R architecture for our DAC design

 

3.2 Why does C1 still use pcm 1704 DAC chip? That chip has been released for quite a long time.

PCM 1704 is a R2R chip and in our opinion, by putting all resistors together onto one chip can make the error much smaller. One can also surely use resistors to build discrete R2R circuit, but in order to build a 24-bit precision R2R circuit, the error of the resistor must be smaller than 0.00001%. This is almost a mission impossible. By comparison, PCM 1704 is a better choice. Although PCM 1704 is discontinued at the moment, we have purchased plenty of them in stock. It will be no problem for further production or maintenance of C1.

 

3.3 Why do you use 4 PCM 1704 chips on each channel?

In each channel, we divide four PCM 1704 chips into two groups. It can form a full balance architecture, while on the other hand, we can take advantage of dithering to eliminate the digital noise so as to reduce the total harmonic distortion, making the beautiful sounding R2R more accurate.

[yamamoto2002]

On 2017/4/15 at 3:02 AM, audiventory said:

 

There is too little information for understanding, that he meant as DSD timing error. Need take scheme and discuss it.

Sorry for the late reply. I found the following qualitative description on the book Look-Ahead Based Sigma Delta Modulation by Erwin Janssen, Arthur van Roermund, pp. 30:

 

Quote

Since the modulator can only react on transients in the input after they have happened, there can be momentarily small differences between the input signal and the reconstructed output signal.(snip) if a modulator is close to overload it will often have difficulty following the input signal, and temporarily a relatively large transient error could result. (snip) a slow change in the input signal can be followed with less problems than a high frequency signal. ...

 

Author proposed new measurement method called "transient SINAD" to measure those temporal encoding errors on this book.

[audiventory]

17 hours ago, yamamoto2002 said:

Sorry for the late reply. I found the following qualitative description on the book Look-Ahead Based Sigma Delta Modulation by Erwin Janssen, Arthur van Roermund, pp. 30:

 

 

Author proposed new measurement method called "transient SINAD" to measure those temporal encoding errors on this book.

 

Thank you for information.

[Miska]

On 4/30/2017 at 4:33 PM, mmerrill99 said:

That's one point about why Miska's FFT plot initially shown & annotated as "less bad 'good' jitter" may not be fully accurate.

 

That is uncorrelated random jitter and thus less bad than correlated sources. Absolute level in this case is also several decades lower than in my example of "bad jitter".

 

So first check that there are no spurious correlated jitter spikes/sidebands and then you can begin to worry about phase noise. In many cases there are clear discrete sidebands... I've measured some DACs that claim to have very low jitter clocks, but then fail by having spurious sidebands due to EMI/RFI leakage to the clock lines.

 

[Miska]

On 5/11/2017 at 3:09 PM, mansr said:

This makes very little sense, if any. Multi-bit sigma-delta modulators are used to improve the noise shaping performance. It has nothing to do with electrical noise in the chip. These aspects are simply not related whatsoever. This statement reads like Mr Smith is making up plausible-sounding excuses in defence of a design approach he favours. I'm not saying his designs aren't good, perhaps even better than many single-chip solutions, but the reasoning above is still bogus.

 

In my opinion, only reason to use multi-bit modulators is to allow simplifying the modulator design (like TI's 3rd order) and thus doing cost-cutting. There are so few bits still in those modulators (like TI's 5-level) that it really doesn't make notable difference compared to dynamic range needed by music... Or for example Chord Mojo that also has high rate multi-bit modulator but ends up delivering noise performance that is not any better than any DSD256.

 

For example with the AKM's new SRC chip I was expecting much better PCM-to-DSD performance than it actually delivers... While the old 1-bit 64fs "DSD" DAC chip, CS4328 delivers better performance than the age would leave one to expect...

 

[louisxiawei]

Just realized that I haven't finish the translation, quite busy during the last few months. Now I have some free time and will end this properly. 

 

Interview with Florian Cossy from CH Precision

 

3.4 Before D-A conversion, does the signal go through your CH-HiD algorithm?

Yes, CH-HiD is our own developed DSP technology, before D-A conversion, the algorithm is at 48G/sec floating speed to do the tasks such as signal upsampling, DSD-PCM conversion, resolution optimization. All digital signal will be upsampled by 16 times to 705.6 kHz for 44.1K based or 768kHz for 48 kHz format and then go into R2R circuit to do the D-A conversion.

 

 

3.5 Do you use your own DSP to do the DSD to PCM conversion?

General media players on PC have function of DSD->PCM conversion and we are not against this approach. However, CH-Hid can direct convert DSD to 705.6 kHz this high-resolution PCM format, which can better preserve the wide frequency response of DSD.

 

3.5 Does C1's volume control also use DSP digital control?

 C1’s volume control is neither digital nor analogue, but a hybrid one. At high volume, we use DSP to do the control at 32-bit signal resolution, so as to eliminate the issue of resolution loss normally caused by digital volume control. At low volume, the control is conducted by the analogue volume attenuation formed by resistors and relay array. For medium volume, DSP and analogue control will work simultaneously. This design will allow lowest noise, lowest phase distortion and biggest frequency response. We consider it as more ideal volume control compared to others and advise customers use our C1 as preamplifier.

 

3.6 What's special of your C1's clock?

C1 is equipped with two VCXO precise quartz oscillator (22.5792Mhz, 24.576Mhz) to separately control 44.1kHz and 48kHz sampling base while controlling the frequency and phase (phase accuracy at +/-. 5us). These two oscillators have their own separate power supply and are located at the place very close to DAC chip. By doing this can therefore enhance the precision of time at spectrum of 0.1Hz/0.1 PPM.

 

3.7 Which is a better interface on your C1? USB or Ethernet?

 

They are equally good but must be under two premises:

1) The signal receiving end must be in the mode of nonsynchronous transmission. In this way, the clock in D-A domain can unified the clock signal and not being affected by the interference of jitter coming from the PC.

2) When using USB as data transmission, the receiving end must have the isolation approach of power supply noise so as to eliminate the power noise pollution from the PC.

Under these conditions, no matter USB or ethernet interface, the digital data is transmitted in packet form to ensure not a single signal is lost. Plus, the clock is controlled by C1, there will be no difference between these two interfaces.

 

3.8 Could you please explain your three-level analogue output on C1 in detail?

 

The analogue output of general DAC has two levels. First level is filtering, this level will not only significantly limit the bandwidth but also put filter in the feedback loop and distort the phase. Hence, our unique design is optimised as three level output line. There is no filtering in the first level, and just pull the bandwidth to 150 MHz, then comes into the second level which is a passive filtering line and lastly send signal to the third analogue output. We believe this design can solve the problems of normal two-level analogue ouput.

The analogue output of C1 has a dual monaural analogue line level, full crystal discrete architecture (without using any OP), overall zero negative feedback design and very low noise and high-slew rate characteristics. Our A1 amplifier is also built based on C1’s analogue output line design.

 

Interview of CH prevision has been fully translated. One last bit to go: MSB.

[rredline]

On Mon Aug 21 2017 at 6:42 PM, louisxiawei said:

Interview with Florian Cossy from CH Precision

 

3.8 Could you please explain your three-level analogue output on C1 in detail?

 

The analogue output of general DAC has two levels. First level is filtering, this level will not only significantly limit the bandwidth but also put filter in the feedback loop and distort the phase. Hence, our unique design is optimised as three level output line. There is no filtering in the first level, and just pull the bandwidth to 150 MHz, then comes into the second level which is a passive filtering line and lastly send signal to the third analogue output. We believe this design can solve the problems of normal two-level analogue ouput.

The analogue output of C1 has a dual monaural analogue line level, full crystal discrete architecture (without using any OP), overall zero negative feedback design and very low noise and high-slew rate characteristics. Our A1 amplifier is also built based on C1’s analogue output line design.

The cost of CH Precision's DAC is high, but some of their design choices does make sense.