CLOCKS, what should we look for in next generation

[jabbr]

39 minutes ago, barrows said:

But I would like to try something better here anyway, just to satisfy my curiosity.  If I did then hear a difference I do have access (not really super easy access) to an AP for testing the DAC output...

 

Sure but I’ve been briefly browsing the Cybershaft site and some people claim to hear life changing differences between clocks that have -120 dBc/Hz @ 1 Hz vs -121 dBc/Hz @ 1 Hz ... so if 1 dB at that level is life changing, then there is no end to the number of clocks you’d need to test in order to satisfy a continued quest for ultimate sound. ... seems like Alice in Wonderland and perhaps it’s easier to injest mushrooms 🍄 

[barrows]

33 minutes ago, Miska said:

 

I'd be curious to see J-test24 results for various different clock modules if you can easily swap them!

 

Yeah, well if I could get the desired "better" clock it would be possible.  Unfortunately the one XO which used to be available (Pulsar Clock) is no longer, and I am not aware of other drop in clocks with this kind of performance/price at audio frequencies without having a custom frequency run done with MOQs I could not afford...

Anyone know of alternative XOs at 45.1584 MHz with < -115 dBc/HZ @ 10 Hz spec (confirmed performance) to the Pulsar Clock at anything close to reasonable prices?  NDK DuColon is too expensive...

The DAC for testing uses a socket, so clocks can drop in...

[PeterSt]

33 minutes ago, Miska said:

I'd be curious to see J-test24 results for various different clock modules if you can easily swap them!

 

Define the output noise level first. 

[barrows]

5 minutes ago, PeterSt said:

 

Define the output noise level first. 

You mean the analog noise floor of the DAC?  I would not do it first, as I have to ship the DAC to where the AP is for testing, but then the full range of tests can be done.

I would add in terms of the J-Test, I am generally more interested in the spread of the skirt than the floor and sidebands (unless they are rather extreme)...

[Miska]

2 minutes ago, PeterSt said:

Define the output noise level first. 

 

No need, we can look at the plots side by side. Same DAC, different clocks...

 

 

[Miska]

7 minutes ago, barrows said:

I would add in terms of the J-Test, I am generally more interested in the spread of the skirt than the floor and sidebands (unless they are rather extreme)...

 

Of course there must be no side bands at all, otherwise you have correlated jitter which comes from clock line interferences (usually PSU or PCB design).

 

So far, one of the best figures I've got is from Holo Spring 2 running at DSD256. And no COTS DAC chips, but just a discrete implementation.

[PeterSt]

15 minutes ago, barrows said:

I would add in terms of the J-Test, I am generally more interested in the spread of the skirt than the floor and sidebands (unless they are rather extreme)...

 

... Nah ... unless the noise is extreme. And I mean so high that no skirts / lobes etc. can be seen. But I think Miska just showed that, despite ...

 

15 minutes ago, Miska said:

No need, we can look at the plots side by side. Same DAC, different clocks...

 

So hmm.

 

The noise floor must be lower to see anything. That's what I meant.

[Miska]

8 minutes ago, PeterSt said:

... Nah ... unless the noise is extreme. And I mean so high that no skirts / lobes etc. can be seen. But I think Miska just showed that, despite ...

 

 

So hmm.

 

The noise floor must be lower to see anything. That's what I meant.

 

Good if you can show better ones (no peaks going above -155 dBr) and narrower main lobe! Let's collect the better ones here, OK?

 

[PeterSt]

4 minutes ago, Miska said:

Good if you can show better ones

 

Barrows is going to show a better one. But you wouldn't be able to tell ...

Anyway let's not be silly. You now know what I meant with the noise level and why.

 

35 minutes ago, barrows said:

(Pulsar Clock)

 

And that one would be better, normally.

[barrows]

22 minutes ago, Miska said:

 

Of course there must be no side bands at all, otherwise you have correlated jitter which comes from clock line interferences (usually PSU or PCB design).

 

So far, one of the best figures I've got is from Holo Spring 2 running at DSD256. And no COTS DAC chips, but just a discrete implementation.

Yes, wish Holo would put a good volume control in their DACs I might just pick up one of those then.  I am scared to rely just on HQP VC.  My DSC-2 build with analog VC from Pavel's board is coming along well...

[Miska]

Some to compare against:

https://www.stereophile.com/content/chord-electronics-dave-da-processor-measurements

https://www.stereophile.com/content/chord-electronics-qutest-da-processor-measurements

https://www.stereophile.com/content/dcs-vivaldi-digital-playback-system-measurements

https://www.stereophile.com/content/dcs-rossini-player-rossini-clock-measurements

[Miska]

3 minutes ago, PeterSt said:

Barrows is going to show a better one. But you wouldn't be able to tell ...

Anyway let's not be silly. You now know what I meant with the noise level and why.

 

No, you sound like you have better ones!  So I'm just waiting to see the better ones without handswaving...

 

I've seen lower noise floors, but with peaks that would still also pop up from this one (higher than -155).

 

[ferenc]

1 hour ago, barrows said:

Yes, wish Holo would put a good volume control in their DACs I might just pick up one of those then.  I am scared to rely just on HQP VC.  My DSC-2 build with analog VC from Pavel's board is coming along well...

 

Actually, I feel stupid.  . 

 

I tried the Holo Spring 2 KTE connected directly to my active desktop studio monitors, and using HQP volume control . It was really good with DSD256 and DSD512 and 786 kHZ PCM too. 

 

Then I switched HQP to Direct SDM. 

Connected my Roger Mayer 456  AnalogTape Simulator as a preamp. It was better every way. More air, more body even better controlled low-end. Very surprising. It is a "coloring" box. But made the music even more entertaining, more emotional, partly and possibly because of the direct SDM beside the very tricky analog processing in the 456?

 

[Miska]

1 hour ago, barrows said:

Yes, wish Holo would put a good volume control in their DACs I might just pick up one of those then.  I am scared to rely just on HQP VC.  My DSC-2 build with analog VC from Pavel's board is coming along well...

 

My headphone amp is set to low gain, so the volume pot in normal listening is around 12. Probably wouldn't be excessively bad with full volume either and thus quite safe with software volume too.

 

With HQPlayer Embedded I'm much less worried since the OS doesn't run or have any other audio applications or sounds. But on Windows or macOS I would be more nervous. With Resonessence Labs HERUS (headphone DAC) on Windows I have several times accidentally blasted full volume to headphones - and it can put out quite loud!

 

On my loudspeaker system I have a preamp anyway, with all it's 8 inputs in use with different DACs...

 

But of volume controls, T+A DAC8 DSD has relay based stepped attenuator that can be switched on/off. Some other devices likes Marantz traditionally have two separate outputs, fixed and variable which is also a nice approach.

 

[jabbr]

2 hours ago, barrows said:

Yes, wish Holo would put a good volume control in their DACs I might just pick up one of those then.  I am scared to rely just on HQP VC.  My DSC-2 build with analog VC from Pavel's board is coming along well...

 

 

Everyone wants femtosecond jitter, right? Does it matter? Everyone says they can tell as soon as they pluck in a femtosecond clock onto a board.

 

So let's look at this. First there was a thread a little while ago where we were talking about the optimal upsampling frequency. Yes the phase error increases with increase clock frequency (all else equal of course). On the other hand, assuming DSD for simplicity sake, the number of samples also increases and these average out.

 

So we are assuming the the averaging doesn't average out jitter ... my calculations indicate that the jitter is averaged out more than the clock jitter increases and I believe significant DSD upsampling reduces the effects of jitter. The calculations were in the previous thread if anyone wants to go through this.

 

Ok so let's assume jitter is important, but in a design similar to DSC --- and I'm NOT using this because its particularly sensitive to jitter, rather because it is a published design that can be analyzed mathematically, and so useful for this discussion -- in a design similar to DSC, the data and clock are distributed to shift registers implement a FIR averaging filter. 

 

So light travels 0.3mm in a picosecond which means that the clock is distributed to each shift register at a phase which is dependent on the path length between the clock and the shift register -- more or less than 0.3mm?  Fact is it is substantially more, so there are multipicosecond variations i.e. skew. Moreover there isn't a proper clock distribution buffer so there are all sorts of reflections bouncing around, and what is the impedance of the  clock distribution trace?

 

So really we are worried about a few femtoseconds of clock jitter? and you want to use SQ to decide? Really? What about all the folks who heard massive improvements reclocking a motherboard? ... oh and who had spread spectrum turned on!

 

Oh yeah that's right: a worse clock might cause the board to give off less EMI! Maybe that's why external clocks with wires floating around sound better  

[zephyr24069]

3 hours ago, jabbr said:

 

Sure but I’ve been briefly browsing the Cybershaft site and some people claim to hear life changing differences between clocks that have -120 dBc/Hz @ 1 Hz vs -121 dBc/Hz @ 1 Hz ... so if 1 dB at that level is life changing, then there is no end to the number of clocks you’d need to test in order to satisfy a continued quest for ultimate sound. ... seems like Alice in Wonderland and perhaps it’s easier to injest mushrooms 🍄 

That would be impossible to hear the difference...there might well be other variables at play.

[mansr]

11 minutes ago, jabbr said:

So light travels 0.3mm in a picosecond which means that the clock is distributed to each shift register at a phase which is dependent on the path length between the clock and the shift register -- more or less than 0.3mm?  Fact is it is substantially more, so there are multipicosecond variations i.e. skew. Moreover there isn't a proper clock distribution buffer so there are all sorts of reflections bouncing around, and what is the impedance of the  clock distribution trace?

Modern high-speed PCB design takes all that into account, from sub-mm trace length matching to correct impedances. Things like multi-GHz PCIe wouldn't work otherwise. There's no reason a DAC board couldn't be designed with the same care. Most of them probably aren't, of course.

[jabbr]

3 hours ago, barrows said:

You mean the analog noise floor of the DAC?  I would not do it first, as I have to ship the DAC to where the AP is for testing, but then the full range of tests can be done.

I would add in terms of the J-Test, I am generally more interested in the spread of the skirt than the floor and sidebands (unless they are rather extreme)...

 

What is the frequency resolution of the AP? At the levels of phase error under discussion you want to have sub-Hz resolution.

 

Some pointers: http://www.ke5fx.com/ke5fx_mud2010.pdf

(note the HP 8662/3 signal generator is awesome! also see 8561/2 spectrum analyzers -- ha ha but finicky  

[fas42]

Just to note that I have never done anything directly to improve the behaviour of a clock; but this has never got in the way of getting the quality of sound  I chase - I suspect this has cherry on top benefits; plenty of other low hanging branches to clear away first ...

[barrows]

53 minutes ago, jabbr said:

 

What is the frequency resolution of the AP? At the levels of phase error under discussion you want to have sub-Hz resolution.

 

Some pointers: http://www.ke5fx.com/ke5fx_mud2010.pdf

(note the HP 8662/3 signal generator is awesome! also see 8561/2 spectrum analyzers -- ha ha but finicky  

As we still see, even in J-Test amongst some very good DACs (Jussi posted examples above) clearly there are differences.  My suspicions are also that the ancient J-Test approach (designed originally to test jitter on SPDIF interfaces, which are generally at higher levels, especially back then, think the nearly ubiquitous CS SPDIF receiver chip, pre-Wolfson, which  has >200 pS of added jitter) is inadequate to really measure where we are at now with the best DACs.

I certainly have heard differences from solely changing clocks from something good, to something just a little better, and no not with some weird flying lead contraption!  Just dropping in another clock to a socket (and before you suggest something here, I am not sure a socket will result in the best performance either, but it will degrade both clock signals equally).

 

As I regard subjective testing as being important if done carefully, i would not be so quick to dismiss the possibility of better clocks actually improving performance of a DAC.  I am not going to just agree with saying that the Crystal 575/957 parts are as good as it gets for DAC performance without further investigation, as too many times things which appear to not matter at first, have been proven to matter later.

 

For the more technically minded folks, say if one were to suggest that the J-Test is antiquated, is there, perhaps, a better testing protocol to look at the effects of clock performance on DAC performance, at the analog output?

 

Got to back to work now, out with soldering iron...

[Miska]

51 minutes ago, jabbr said:

Ok so let's assume jitter is important, but in a design similar to DSC --- and I'm NOT using this because its particularly sensitive to jitter

 

Is it? Seems to be among other SDM DACs, not being particularly sensitive to jitter, thanks the multiple unity weighted elements.

 

R2R DACs tend to be much more, lower the rate they run at, more sensitive they become.

 

54 minutes ago, jabbr said:

So light travels 0.3mm in a picosecond which means that the clock is distributed to each shift register at a phase which is dependent on the path length between the clock and the shift register -- more or less than 0.3mm?  Fact is it is substantially more, so there are multipicosecond variations i.e. skew.

 

This is static variable, so not related to jitter. And actually that static skew is a good thing, it makes it perform better! If you want to optimize it, you'd make 1/4th clock period skew between each register - which you could do with a rotator and 4x higher MCLK.

 

56 minutes ago, jabbr said:

Moreover there isn't a proper clock distribution buffer so there are all sorts of reflections bouncing around, and what is the impedance of the  clock distribution trace?

 

Output logic has enough fan-out. At these clock frequencies it is not really a problem... You have not dealt with 80's computer designs with through-hole DIL chips on FR4 boards?

 

 

The original DSC1 design has couple of problems I'm planning to fix, but those are not clock related...

[fas42]

To get an idea of what they're chasing in speed capabilities at the moment ...

 

https://www.google.com/search?tbo=p&amp;tbm=bks&amp;q=terahz&amp;num=100

[Miska]

14 minutes ago, barrows said:

As we still see, even in J-Test differences amongst some very good DACs (Jussi posted examples above) clearly there are differences.  My suspicions are also that the ancient J-Test approach (designed originally to test jitter on SPDIF interfaces, which are generally at higher levels, especially back then, think the nearly ubiquitous CS SPDIF receiver chip, pre-Wolfson, which  has >200 pS of added jitter) is inadequate to really measure where we are at now with the best DACs.

 

I don't think it is inadequate at all. It would be inadequate if everybody would get exactly same perfectly clean result. It is very good also for testing I2S interference from data lines to the clock lines. But as long as there are huge differences between DACs with this measurement we have a very good measurement tool at hand.

 

But for example my original DSC1 proto is certainly much much better than those old S/PDIF interfaces or R2R NOS DACs running at 44.1k!  Not nearly as good as the Holo Spring 2 though which is again much much better (just don't run it NOS @44.1k).

 

14 minutes ago, barrows said:

For the more technically minded folks, say if one were to suggest that the J-Test is antiquated, is there, perhaps, a better testing protocol to look at the effects of clock performance on DAC performance, at the analog output?

 

I don't think there's an immediate need for something else at the moment, so I haven't been actively looking... I think the current test is quite cleverly designed and simple enough as well.

 

[barrows]

@Miska, I will defer to your expertise then!

[jabbr]

17 minutes ago, Miska said:

Is it? Seems to be among other SDM DACs, not being particularly sensitive to jitter, thanks the multiple unity weighted elements.

 That came out wrong!

 

I didn't select to use DSC as an example of a phase noise sensitive DAC, rather I am using DSC as an example simply because the schematic is publicly available. 

 

Agreed that the averaging with the multiple elements reduces the sensitivity to jitter and I also maintain that upsampling, by similarly increasing the number of samples, further reduces the sensitivity to jitter.