Discussion of the UpTone / J.Swenson EtherREGEN 'white paper'

[JohnSwenson]

1 hour ago, lmitche said:

Hi guys,

 

Here is dumb question number one and two!

 

The paper states that the clock timing is the same regardless of "noise".

 

Understanding that, if the state change threshold is at 2 volts and the ground pane noise pushes the threshold voltage to 2.1 volts, won't a 2 volt "bit" go undetected? Likewise, assuming the noise can also lower the threshold, to say 1.9 volts, could not "bits" be detected that don't exist?

 

Just curious.

 

Larry

The thresholds are usually set so they are somewhere in the middle between the low voltage and high voltage of the signal. The idea here is that there can be large amounts of noise and the "data" (the ones and zeros) still get recovered properly.

 

In many digital technologies the thresholds actually do change a little. In these technologies the threshold is a ratio between VSS and VDD (power and ground pins). So changes on the power pins can actually cause a change in the threshold. (there is actually a ton of stuff that can happen inside a chip, but I didn't want to get too far down THAT rabbit hole in this paper)

 

John S.

 

 

[JohnSwenson]

4 hours ago, firedog said:

 

Am I missing something here? The critics' demand has always been for measurements showing the analog output of the DAC is affected by the various types of noise. Showing that the noise arrives to the DAC isn't going to answer that question. 

Correct, I'm working on DAC output as well. None of this stuff is easy. We are trying to measure a DAC output using ADCs, to do that requires an ADC that has lower clock jitter than the DAC we are trying to measure, this is NOT easy to do! The off the shelf audio analyzers are nowhere near close enough. So as with everything else related to this I have to make my own. It's not easy and it's not cheap.

 

I have something up and running which still needs a lot of more work to lower ADC jitter and prevent external signals from getting in, but it DOES actually get signal through. Maybe within the next week I'll try it with real audio DACs and see how things are at this point in the development process.

 

My ultimate goal is to show the whole process from ground plane noise, to DAC clock jitter to DAC analog output.

 

I WILL get there, but it is going to take a significant amount of time to get there.

 

John S.

[JohnSwenson]

I made several attempts at this but could never build a measurement system that had significantly lower phase and amplitude noise than what I was trying to measure. If your measurement system has more noise than what you are trying to measure no measurements are valid.

 

The measurement system consists of two channels of high bit (24 or more) and high frequency ADCs, being clocked by an extremely low phase noise clock. Just this part is hard enough to do, but not impossible. The hard part is getting this huge amount of data out of the ADC without adding noise to the clock signal and the circuits inside the ADC. I have tried several different approaches that did not succeed. (they get the data out but add too much extra noise in the process) It looks like what I am going to have to do is use ADCs with a very high speed single differential pair carrying all the data, feed that through an SFP+ module -> fiber -> SFP+ module to FPGA with extremely fast SERDES that can store the data to high speed RAM chips, then when sampling is done write SD card etc. Both sides of this need their own battery powered system. The whole thing in a sealed, shielded enclosure. It is getting to the point that all the components of this are coming available without costing half a million dollars. In the next year the parts to do this will probably be available for less than $10K, BUT it will be a long process to develop this.

 

It will happen but it might be several years.

 

John S.