HQ Player

[Chris PRaT]

To whom it concerns,

 

The issue I previously mentioned concerning a light static/background noise when using HQP DSD256 -> USB input of SMSL VMV D2 DAC, either wired or via wifi to NAA, was fixed by using a DDC -> I2S input of DAC.

 

No more background noise!  

 

Thanks to those who helped me out and who taught me how to download an ASIO driver ;)

[Miska]

3 hours ago, dericchan1 said:

Hi Miska, I have a Marantz HDAMP1 that uses a ESS Sabre 9010K2M chip and supports upto 32/384 or dsd 11.2 what would be the recommended HQPlayer setting for this? SDM or PCM? Thanks

 

Either 384 PCM with 32-bit TPDF/Gauss1 dither, or DSD256 with ASDM5EC(v2) modulator.

 

[dericchan1]

16 minutes ago, Miska said:

 

Either 384 PCM with 32-bit TPDF/Gauss1 dither, or DSD256 with ASDM5EC(v2) modulator.

 

Thanks Miska, if I upsample to 32/384 pcm, am I likely still not bypassing the base and sampling filters?

 

Deric

[Fredc]

1 hour ago, Miska said:

 

Either 384 PCM with 32-bit TPDF/Gauss1 dither, or DSD256 with ASDM5EC(v2) modulator.

 

For the sigma delta dac, wouldn't dsd input be more direct. 

[TJHUB]

21 minutes ago, Fredc said:

For the sigma delta dac, wouldn't dsd input be more direct. 

 

It might be, but on my ESS DAC, 32/384 sounds better than DSD.  Both should be listened to, and pick the one that sounds best.

[TJHUB]

Jussi:. I have 2 friends that have the same Eastern Electric ESS 9018 DAC as I do.  Weeks back I found 32 bits to be necessary for PCM to sound its best.  I found this by setting DAC Bits to "default" which always sends 32 bits on the output.  

 

I got my 1st friend up and running on HQP with the same DAC Bits setting of "default".  He too gets 32 bit output every time.  He will be a new customer any day now.

 

I got my 2nd friend up and running about an hour ago.  To get his current gear to test HQP, I have his i5 4th gen audio PC that is too old to run HQP setup as an NAA with the x64ramfs bootable USB stick.  The only machine he has that will run HQP is an i7 8th gen laptop.  Everything is working but he gets 24 bit output whether the DAC Bits setting is set to "default" or set to "32".  I don't understand how this is possible?  What might be causing this?  This DAC does not sound good with 24 but output.

 

 

[giordy60]

Jussi
I saw you updated the NAD to version 4.2.0
What's new ?
thank you.

 

apart from this obvious ....

Workaround for certain buggy XMOS USB firmware versions.

[musicjunkie917]

1 hour ago, giordy60 said:

I saw you updated the NAD to version 4.2.0
What's new ?

 

From the web site:

 

"Workaround for certain buggy XMOS USB firmware versions. Component updates and minor fixes."

[bogi]

On my ESS DAC I prefer DSD256. Tastes may be different ...

[Miska]

12 hours ago, TJHUB said:

I got my 2nd friend up and running about an hour ago.  To get his current gear to test HQP, I have his i5 4th gen audio PC that is too old to run HQP setup as an NAA with the x64ramfs bootable USB stick.  The only machine he has that will run HQP is an i7 8th gen laptop.  Everything is working but he gets 24 bit output whether the DAC Bits setting is set to "default" or set to "32".  I don't understand how this is possible?  What might be causing this?  This DAC does not sound good with 24 but output.

 

You can count that in as having one of the buggy XMOS USB interfaces then... Try with the 4.1.3 or 4.2.0 ramfs stick...

 

If he still gets 24-bit, then the buggy one is likely Windows driver or what ever the other one uses.

 

[Miska]

13 hours ago, dericchan1 said:

Thanks Miska, if I upsample to 32/384 pcm, am I likely still not bypassing the base and sampling filters?

 

Not entirely, with DSD inputs you get past the rate conversions (as long as the chip is running in synchronous clocking mode).

 

For example SMSL seems to run in synchronous mode with ASRC disabled, with dual clocks, one for each rate family. While Topping seems to run in asynchronous mode with ASRC active, out of single (100 MHz?) clock.

 

[dericchan1]

27 minutes ago, Miska said:

 

Not entirely, with DSD inputs you get past the rate conversions (as long as the chip is running in synchronous clocking mode).

 

For example SMSL seems to run in synchronous mode with ASRC disabled, with dual clocks, one for each rate family. While Topping seems to run in asynchronous mode with ASRC active, out of single (100 MHz?) clock.

 

I read on the product page that usb runs in asynchronous mode.

 

 

[Miska]

26 minutes ago, dericchan1 said:

I read on the product page that usb runs in asynchronous mode.

 

That's the USB interface, that's the case always on modern DACs. But I'm not talking about USB interface, but instead the DAC chip's clocking.

 

ESS DAC chips have an ASRC (Asynchronous Sample Rate Converter) and can run with this enabled, from single fixed frequency clock - typically 100 MHz. Regardless of source rate family. You can also disable this ASRC and run from rate family specific clock, typically for example 45.1584 MHz for 44.1k-base rates and 49.152 Mhz for 48k-base rates.

 

[dericchan1]

5 minutes ago, Miska said:

 

That's the USB interface, that's the case always on modern DACs. But I'm not talking about USB interface, but instead the DAC chip's clocking.

 

ESS DAC chips have an ASRC (Asynchronous Sample Rate Converter) and can run with this enabled, from single fixed frequency clock - typically 100 MHz. Regardless of source rate family. You can also disable this ASRC and run from rate family specific clock, typically for example 45.1584 MHz for 44.1k-base rates and 49.152 Mhz for 48k-base rates.

 

I see, thanks Miska!!!

[TJHUB]

1 hour ago, Miska said:

 

You can count that in as having one of the buggy XMOS USB interfaces then... Try with the 4.1.3 or 4.2.0 ramfs stick...

 

If he still gets 24-bit, then the buggy one is likely Windows driver or what ever the other one uses.

 

 

My friend had already tried the updated NAA image and it worked.  I'm surprised I don't have the same issue, and I'm still running the old image.  Thank you though!

[copy_of_a]

2 hours ago, Miska said:

For example SMSL seems to run in synchronous mode with ASRC disabled, with dual clocks, one for each rate family. While Topping seems to run in asynchronous mode with ASRC active, out of single (100 MHz?) clock.

@Miska 2 related questions...

 

Recently I bought an SMSL DAC (M500 MKII) for my Desktop with ES9038pro chipset that only does 44.1x DSD rates (run it from a Mac through USB via DoP), it does not handle incoming 48x DSD rates.

 

Question regarding PCM playback and software upsampling.
We are talking delta sigma DAC, so of course all incoming PCM input is upsampled internally to DSD before converted to analog.
Now, when the DAC can only handle 44.1k DSD rates does that consequently also mean incoming 48k, 96k, 192k etc. PCM rates get non-integer upsampled to a multiple of 44.1kHz inside the DAC? And if so, wouldn't it be better to upsample PCM to the highest 44.1kHz based rate instead of the highest available rate - so for instance to 705.6kHz instead of 768kHz?

And a question regarding DSD playback.
Am I correct assuming that incoming lower DSD rates (DSD64, DSD128) do not get further upsampled internally in a ES9038pro based DAC (in my M500MKII respectively) to the highest DSD rate?

Many thanks in advance!

[Miska]

1 hour ago, copy_of_a said:

@Miska 2 related questions...

 

Recently I bought an SMSL DAC (M500 MKII) for my Desktop with ES9038pro chipset that only does 44.1x DSD rates (run it from a Mac through USB via DoP), it does not handle incoming 48x DSD rates.

 

I have the same device too, fed by iFi Zen Stream.

 

1 hour ago, copy_of_a said:

Question regarding PCM playback and software upsampling.
We are talking delta sigma DAC, so of course all incoming PCM input is upsampled internally to DSD before converted to analog.
Now, when the DAC can only handle 44.1k DSD rates does that consequently also mean incoming 48k, 96k, 192k etc. PCM rates get non-integer upsampled to a multiple of 44.1kHz inside the DAC? And if so, wouldn't it be better to upsample PCM to the highest 44.1kHz based rate instead of the highest available rate - so for instance to 705.6kHz instead of 768kHz?

 

No, the DAC doesn't convert 48k-base inputs to 44.1k-base. The lack for support for 48k-base DSD inputs is just strange artificial limitation in the USB interface firmware. There's really no technical reason for it.

 

You get a bit of advantage running it always at 768k.

 

Note that the device has USB interface bug that after power up you need to stick to these 16x rates if you want to use them. If you switch to any lower rate at any point and come back it will start misbehaving and you need to power it down and start it again to get the behavior fixed!

 

This is opposite of the bug iFi Micro iDSD has where you instead need to play lower rate once before going to 16x rate or it will misbehave.

 

1 hour ago, copy_of_a said:

And a question regarding DSD playback.
Am I correct assuming that incoming lower DSD rates (DSD64, DSD128) do not get further upsampled internally in a ES9038pro based DAC (in my M500MKII respectively) to the highest DSD rate?

 

Yes, based on all information I have, no sample rate conversion is performed for DSD (as long as the ASRC is not active).

 

Also DSD512 works fine with the M500 mkII with the same caveat as 16x PCM rates.

 

[copy_of_a]

Super - thank you so much Miska!!

 

2 hours ago, Miska said:

I have the same device too, fed by iFi Zen Stream.

cool, neat slick setup!

The M500 MKII first got my attention due its form factor. Brilliant on a desktop!

 

Since you have the same device may I also ask you how you've set the DPLL (Anti-Jitter) setting?

I've set mine to minimum and everything works fine (also on another SMSL DAC with the same chip).

 

2 hours ago, Miska said:

No, the DAC doesn't convert 48k-base inputs to 44.1k-base. The lack for support for 48k-base DSD inputs is just strange artificial limitation in the USB interface firmware. There's really no technical reason for it.

 

You get a bit of advantage running it always at 768k.

Thanks for clarifying - much appreciated!

 

2 hours ago, Miska said:

Note that the device has USB interface bug that after power up you need to stick to these 16x rates if you want to use them. If you switch to any lower rate at any point and come back it will start misbehaving and you need to power it down and start it again to get the behavior fixed!

My goodness - thanks for letting me know!!🙏

By now only used it at lower PCM rates and DSD so I didn't notice!

One has to wonder how they sell such stuff. But as long as there's a workaround I can certainly live with it.

 

 

2 hours ago, Miska said:

Also DSD512 works fine with the M500 mkII with the same caveat as 16x PCM rates.

can't go to DSD512 to date but very good to know that the same bug applies!

 

While we're at it. I think my personal taste is somewhat against the trend here.
I almost always prefer prefer DSD64 over DSD128 or DSD256 - at least with EC modulators.
This applies to my old DAC with double mono Ti/BB PCM1792 chips and also to said ESS chips... so obviously independent of the DAC for me.
It actually puzzles me. I've always ruled out DSD64 due to what I've been reading about it here and elsewhere regarding its noise shape and the filtering required etc. But some months ago simply tried it with EC modulators and really prefer DSD64 over higher rates. It's as detailed and clean as higher rates but sounds ever so slightly more snappy, meaty, lush and less thin, especially perceptible with drums. Talking subtle nuances, of course, but for me they are there. There's no distortion or empasis of anything that I am aware of ... I actually perceive it as a better timing and overall more coherent. For classical music, though, I think I prefer higher rates. But since I am too lazy I always leave things at DSD64 and only somtimes change the SRC filter

Can there be a technical reason for this or is this simply pure imagination on my side?

 

Thanks a lot again!!! 👍

 

[fgribas]

2 hours ago, Miska said:

 

I have the same device too, fed by iFi Zen Stream.

 

 

This is opposite of the bug iFi Micro iDSD has where you instead need to play lower rate once before going to 16x rate or it will misbehave.

 

I have a portable DAC (SMSL Idea) that has both bugs, really annoying.

 

Do you have any kind of list of DACs known for a buggy XMOS USB interface? Sorry if it was already mentioned, I've been away for so long.

[Miska]

5 hours ago, copy_of_a said:

Since you have the same device may I also ask you how you've set the DPLL (Anti-Jitter) setting?

 

Eehh, I don't know... Where is such setting?

 

5 hours ago, copy_of_a said:

One has to wonder how they sell such stuff. But as long as there's a workaround I can certainly live with it.

 

I have a feeling that nobody is actually thoroughly testing these things at SMSL and Topping. I'm finding so many strange quirks, that one really needs to be careful how to use these. All advertised things don't really work. Large portion of the problem is XMOS firmware with the MQA stuff.

 

5 hours ago, copy_of_a said:

While we're at it. I think my personal taste is somewhat against the trend here.
I almost always prefer prefer DSD64 over DSD128 or DSD256 - at least with EC modulators.
This applies to my old DAC with double mono Ti/BB PCM1792 chips and also to said ESS chips... so obviously independent of the DAC for me.

 

I think it also comes down to rest of the system; amplifiers, speakers/headphones and so on.

 

[dericchan1]

Hi Miska, what does arbitrary precision math means and what does it do?

 

thanks

 

Deric

[copy_of_a]

5 hours ago, Miska said:

Eehh, I don't know... Where is such setting?

There's a dedicated setting in the menu:

DPLL

 

From the manual:
 

Quote

 

DPLL - MIN ~ MAX

(A total of 15 kinds, the default is 7 kinds. The larger the number is, the stronger the range to adapt to jitter, and the smaller the number, the better the performance against clock jitter.)
This DPLL setting is a special function of ESS series products. It can adjust the internal DPLL digital phase locked loop circuit Bandwidth, so that the chip achieves a balancebetween anti clock jitter and input tolerance.

 

Its function:
When the clock stability of the input signal is good, this value can be reduced, so that the clock performance of the system is better.
When the clock stability of the input signal is not good, the sound may be interrupted.
Increase this value can avoid the sound interruption! Especially when using TV as signal source!

 

 

 

5 hours ago, Miska said:

I have a feeling that nobody is actually thoroughly testing these things at SMSL and Topping. I'm finding so many strange quirks, that one really needs to be careful how to use these. All advertised things don't really work. Large portion of the problem is XMOS firmware with the MQA stuff.

I see. I'll check any time later with my other SMSL DAC as it does not have MQA (SMSL Su-9n)

 

Thanks, Miska!

[bogi]

With Topping E50 I didn't observe XMOS related issues. E50 supports 48k based DSD and correctly switches between 44.1k and 48k based DSD rates although fs information is incorrectly displayed for 48k based DSD - it shows the next 44.1k based value e.g. 11.2 for 48k based DSD128. The only real restriction is that I was not able to switch to 48k based DSD512 (it seems it performs 44.1k based fs comparisons in firmware and thus anything above 44.1k DSD512 it considers unplayable). But since my notebook doesn't have enough power for EC modulators at DSD512 it is no real restriction for me. I still can do 44.1k DSD512 with lighter modulators if I would wish.

[Miska]

5 hours ago, copy_of_a said:

There's a dedicated setting in the menu:

DPLL

 

Ahh, yes, I have it set to "5 Default value". I didn't touch it. I only set PCM filter to "Fast linear" and DSD filter to "50 kHz" and pre mode to fixed (for measurements). But currently I'm running it with HPA-only mode.

 

I think the DPLL value should only matter for S/PDIF inputs where the device is clock slave. There shouldn't be DPLL active when running from local clocks...

 

Here are the Jtest-24 figures I measured with the default DPLL setting for both 352.8k PCM and DSD256:

 

5 hours ago, copy_of_a said:

From the manual

 

I don't think I have ever looked at the manual... 😅

 

[Miska]

17 minutes ago, bogi said:

With Topping E50 I didn't observe XMOS related issues. E50 supports 48k based DSD and correctly switches between 44.1k and 48k based DSD rates although fs information is incorrectly displayed for 48k based DSD

 

I have D90SE, but it has so many problems that it is staying in box (and it wasn't even cheap!)... Certain input signals triggers it misbehave, like in this sweep test at 705.6k rate when input frequency goes over 10 kHz (by the way, same happens with all DSD rate inputs too):

 

When you try 48k-base DSD, check that it is actually running out of 48k clock and not 44.1k clock. Some DACs produce audio just fine with 48k-base DSD, but with wrong clock, so they play at wrong speed and you get pitch shift. Easy to check with accurate enough spectrum analyzer and 1 kHz test tone, that it actually plays at 1 kHz and not at 920 Hz.