Audinate releases Dante IP Core for Xilinx FPGAs

[Miska]

11 hours ago, ferenc said:

 

Clock

• High-quality, low jitter clock with companion Silicon Labs clock generator
• External word clock sync input

 

I'm curious what they define as "low jitter", because these are PLL clocks generated from the network packets...

 

[Miska]

9 hours ago, ferenc said:

They say they have external word clock sync input as well. 

 

Word clock input is very problematic, since it is low frequency system and needs PLL clock generator to create the needed high rate clock. Usually it just worsens jitter performance.

 

[Miska]

1 hour ago, ferenc said:

I hope we will learn more of it soon as the next NAMM show is coming so probably there will be more announcements regarding this solution.

 

Another common standard is AVB, which is very common on car IVI systems and such. I have a Motu 8D, but haven't got time to do much testing with it yet. I'll be anyway using it mostly through USB connection, but since it also has ethernet I'll do some testing through that too.

 

I'm also planning to get Motu LP32 which is variant of the same.

 

XMOS has AVB implementation for their processors.

[Miska]

4 hours ago, jabbr said:

Dante Core would allow a Spartan-6 based DAC such as PS DirectStream to enable Dante input eg https://forums.xilinx.com/t5/Xcell-Daily-Blog/Audiophiles-swoon-over-DirectStream-DSD-audio-DAC-based-on/ba-p/681296

 

Do you think there's free space available in the FPGA for that much extra functionality? I'm quite sure PS DirectStream DSP functionality and Dante both take so much space on the FPGA that they cannot coexist on the same FPGA...

 

But interesting link in itself, that the PS DirectStream uses bunch of cascaded filter sections instead of one single-pass filter...

[Miska]

9 hours ago, jabbr said:

The family has between 3.8k and 147K logic cells, so would depend on which chip. 

 

The 7 series FPGAs range up to 2000k cells, and the Ultrascale up to 5,500k cells so ...

 

Spartan is a very small and cheap FPGA, the cheapest one. Ultrascale stuff is not cheap (and consumes quite a bit of power too) -> heat.

 

Someone once asked me what would it take to run HQPlayer algorithms on FPGA and after calculations I ended up pretty much at the biggest and fastest Virtex models and still couldn't be sure if it'll fit and work. After that they weren't interested anymore...  Such FPGAs cost more than traditional CPU + GPU, and much more costly and difficult to work with.

 

9 hours ago, jabbr said:

The Zynq series include an embedded ARM (dual vs quad core) eliminating the need for the Microblaze CPU. This is what the Merging board uses.

 

I'm more Altera guy...

But I had things running on similar Altera's SoC:

https://www.altera.com/products/soc/overview.html

 

The lightest Cyclone-V SoC is enough for NAA use.

 

9 hours ago, jabbr said:

Perhaps much easier is to run the network stack on the ARM which would enable networkaudiod or a similar protocol, Roon etc. to run the network io, sending buffers to the FPGA -> DSD, PCM or I2S as desired. The FPGA side, for example, can run on an external clock

 

Yes, certainly! Probably that's how Ravenna works too. Those FPGA SoCs are just normal computers with FPGA glue around. Fairly easy to work with and very flexible.

 

[Miska]

5 hours ago, jabbr said:

I think this newer generation of hybrid CPU/FPGA and it’s increasing adoption is an explicit acknowledgement that certain processing is much better done on CPU and other on FPGA, and you can use both more effectively.

 

I see FPGA mostly as flexible I/O glue to be used for simple logic level glue. Not really for any processing.

 

If you want to get to CPU-like clock speeds (sample-rate-to-instruction ratio) of about 4.5 GHz, you will end up with the most expensive and power-hungry FPGAs. And still likely won't achieve those clocks speeds. 102040 clock cycles per 44.1 kHz input sample is quite nice margin to have.

 

[Miska]

9 hours ago, jabbr said:

No I used that as an example of a DAC with the Spartan-6 — if it has Ethernet input and enough free cells then you could add Dante — of course the FPGA would need to be reprogrammed. I think Ayre may also use the Spartan 6 but depends on free cells.

 

I think both are way too full already to have space for such functionality. Dante implementation is probably not among the smallest, probably containing MicroBlaze or some other MCU for the network protocol stack. Trying to do something like DHCP client as pure hardware is pointless.

 

[Miska]

23 hours ago, jabbr said:

Exactly! so putting an Ethernet frame(s) into a buffer — and splitting out the DSD into parallel I/O lines under control of an external clock is very very simple. No need for clocks in the GHz range — Ethernet can go in with a dedicated high speed I/O (eg GTX I think on Altera) — FPGAs used in 100gbe NICs. FPGA makes great IO machine .... math ... err depends.

 

But doing DSD1024 x 16 (saturates 1Gbe) is doable. 

 

Depends what you mean by doing "DSD1024 x16", for me it means doing DSP and delta-sigma modulation for 16 channels of DSD1024...   If you want to run my adaptive modulators at such rates, you'll need GHz clocks.

 

If you just mean shoveling ready-made data around, you are correct.

[Miska]

6 hours ago, jabbr said:

Here I mean accepting and deserialzing that amount of data. I’m saying that’s the limit of what 1gbe can handle, to go above that The take home here is that handling these levels of IO and similar I assume for multichannel Dante/Ravenna can saturate a low end FPGA in and of itself not leaving much for filtering (perhaps). 

 

I don't think this IO bandwidth is problem in this. But just amount of logical blocks used by different functions vs available number of blocks on the FPGA. For example just MicroBlaze MCU alone would take quite a bunch of space.

 

For example the DSP algorithms in DirectStream likely take up so large portion of available blocks that there is hardly space left for something like Dante. This is not about speed, but about size of the functionality.

 

6 hours ago, jabbr said:

Interestingly the highest end “RF SoC” can do multichannel 5ish GHz ADC/DAC — these are for Radar/SDR/Cellular etc. They use some tricks to get the bandwidth higher than the clock rate — mostly parallelizing the problem. ... these chips aren’t cost effective for our purposes 

 

Not every algorithm can be parallelized though. That's also why GPUs cannot help on all things HQPlayer does.

 

[Miska]

1 hour ago, jabbr said:

It depends. e.g.: https://forums.xilinx.com/t5/Networking-and-Connectivity/PHY-transceiver-for-1Gig-Ethernet-connectivity/m-p/219619/highlight/true#M3164

 

Yes you could potentially redesign the board and add an external Ethernet PHY, or, as described, go with a higher-end FPGA which has builtin high speed IO channels (GTP/GTX) and then do the Ethernet PHY in IP. All depends on what you are starting with.

 

Ehm, how is that related? Having something as simple as Ethernet PHY is not so much an issue. You can buy PHY as a separate purpose-built chip.

 

1 hour ago, jabbr said:

Yes you could potentially redesign the board and add an external Ethernet PHY, or, as described, go with a higher-end FPGA which has builtin high speed IO channels (GTP/GTX) and then do the Ethernet PHY in IP. All depends on what you are starting with.

 

Well, Spartan-6 is certainly not higher-end, it is low-end. But ethernet is not so much issues, than the higher level things needed, although ethernet MAC with checksumming offload and such would also take already some space. You certainly want full checksumming offload, zero-copy DMA and such for handling higher channel counts and rates if you use something as low performance as MicroBlaze as MCU. Entire IP protocol stack, PTP protocol, RTP/RTCP/RTSP protocols, DHCP client, etc, etc. All that actually makes up Dante. Ethernet and IP protocol stack are just fundamental basic ingredients that don't yet alone do anything useful.

 

[Miska]

37 minutes ago, Ralf11 said:

Are there any noise or other problems involved in using FPGAs for audiophile purposes?

 

They are relatively power hungry compared to ASICs, or inefficient for CPU implementation. But they are often good replacement for cases where you would need lot of traditional chips like 74-series logics or similar. Depending on compilation result and used I/O pins and block allocation, signal propagation delays vary. So for signal consistency one may need to manually assign logic blocks that are near the I/O pins. For example going to neighboring pin is usually faster than going across the chip.

 

So just like board layout design, you also need to pay attention to on-chip layout design. But you cannot do hand-drawn optimizations like you can with ASIC or PCB design.

[Miska]

2 hours ago, marce said:

Here is an interesting FPGA design, about 4,500 connections, 2,000 pads. The smaller pic shows the DDR differential clock, all the other squiggly bits (as I call them...) are the data bus lanes, address and control signals. This is an extreme design, I will try and find some pics of routers and switches as they tend to be far simpler though...

 

I've done similar stuff for radar things. Board layout was one PITA, but even more so was to make the insides and outside of the FPGA match requirements. Since it's neither alone, but the combination. And FPGA is not as flexible as the board design, it has it's hard constraints... (like, "ahh shit, I need to swap these two pins to make the FPGA work, damn, I need to redesign half of the board too") But that was still relatively small effort compared to the software.

 

This year, HQPlayer is 20 years old and my company is 10 years...

[Miska]

...I did some 3D volumetric processing for sonar systems (passive sonar input) some 10+ years ago. For audio playback that is even older stuff.

 

Now that HQPlayer Embedded supports also realtime audio inputs, it could do some other interesting things too...

[Miska]

6 hours ago, ferenc said:

 

Feature Matrix	Analog Input 1 Ch	Analog Input 2 Ch	Analog Output 1 Ch	Analog Output 2 Ch	USB I/O 2 In 2 Out	AES3 I/O 2 In 2 Out
Signal level	Balanced: +18dBu sine => 0dBFS		Balanced: +24 / +4 / +2.4 / -0.5 / -7.6 dBu @ 0dBFS		-	-
Frequency Response	20Hz to 20kHz (-/+0.5dB)		20Hz to 20kHz (-/+0.5dB)		-	-
Impedance	Input: 20k Ohm balanced or 10k Ohm unbalanced		Output: 150 Ohm balanced or 75 Ohm unbalanced		-	110 Ohm bal­anced
Dynamic Range	> 100dB (unweighted) @ +18dBu		> 100dB		-	-
Signal to Noise Ratio	> 100 dB (unweighted) @ +18dBu		> 100dB		-	> 135dB (un­weighted)
Total Harmonic Distortion	< 0.01% at +4dBu		< 0.01% @ +4dBu		-	-
Channel Separation	-	> 100dB	-	> 90dB	-	-
Channel Matching	-	< 0.25dB	-	< 0.4dB @ 1kHz	-	-
Connectors	RJ45 & 1 x XLR female	RJ45 & 2 x XLR female	RJ45 & 1 XLR male	RJ45 & 2 XLR male	RJ45 & USB Type A	RJ45, 1 XLR male, 1 XLR female
Power	Class 1 802.3af PoE	Class 1 802.3af PoE	Class 1 802.3af PoE	Class 1 802.3af PoE	Class 1 802.3af PoE or USB	Class 1 802.3af PoE
Asyn­chronous Sample Rate Conversion	-		-		-	Yes
Sample Rates	44.1, 48, 96 kHz		44.1, 48, 96 kHz		48 kHz	44.1, 48, 96 kHz
Bit Depths	16, 24, 32		16, 24, 32		24	16, 24, 32
Audio Transport Formats	Dante Audio over IP, AES67 RTP		Dante Audio over IP, AES67 RTP		Dante Audio over IP, AES67 RTP	Dante Audio over IP, AES67 RTP
USB	-		-		USB 2 Full Speed Class 1 Audio	-
Part Number	ADP-DAI- AU-1X0	ADP-DAI- AU-2X0	ADP-DAO- AU-0X1	ADP-DAO- AU-0X2	ADP-USB-   AU-2X2	ADP-AES3- AU-2X2

 

Hmmh, why are all those dongles limited to 96 kHz? And why is the USB dongle fixed to 48 kHz?