Popular Post JohnSwenson Posted March 9, 2019 Popular Post Share Posted March 9, 2019 5 hours ago, rickca said: Clocking is implemented with a technique called DDS (direct digital synthesis) which takes clock induced jitter to immeasurable levels. @JohnSwenson can you explain a bit about DDS? I don't know what this statement is about, DDS has nothing to do with clock generation. DDS is a way to generate (note, not play but generate) an analog wave form such as a sine wave. You have a counter which counts up and down a certain number of bits (8 bits, 16 bits, 24 bits etc). If you feed the output of the counter into a DAC chip you get a triangle wave. Converting into a sine wave is usually done with a look up table. But if the number of bits is high that lookup table can be HUGE. FPGAs are getting good enough that a trigonometric processor can actually do the calculations on the fly, even at very high bit depths. There are a couple of different ways of getting that initial triangle wave. A common one is say have a 32 bit accumulator (register and adder) and a fixed sample rate (44.1, 192 whatever). Every click of the sample clock you add a number into the accumulator. This number changes with the frequency of the sine wave you want to generate. For a higher frequency you use a higher number. This type of circuit has nothing to do with jitter attenuation, the jitter in the clock is directly transmitted to the output. I don't get what DDS has to do with clocking, it's all about generating a specific frequency sine wave, why would you use that for clocking? DDS is great for building a synthesizer (thing with a keyboard and music comes out) but for playing back music I don't get it. I supposed they could be meaning that they use the part about using different numbers into an accumulator to generate word clocks from a high frequency oscillator rather than using an analog PLL. This is usually called a DPLL. This works by having circuitry in the FPGA or processor code change the number sent to the accumulator such that the time that the accumulator overflows is somewhat close to the reference. The problem with this is that if you need fairly fine frequency change you need a very high frequency local clock. The frequency resolution is usually fairly coarse so the output frequency is jumping around rather than smoothly following the input reference. But personally I do not call this "DDS" there is no analog waveform coming out of this. If they are using a Digital Phase Locked Loop, just call it that. They COULD be meaning that they are using a DPLL to generate the internal word clock, that can very well have lower jitter than an analog PLL, but the output frequency will probably be bouncing around. But the jitter is still not immeasurable. The info in the quote doesn't give anywhere near enough info to figure out what is actually happening in the circuit. John S. rickca, johndoe21ro and One and a half 1 1 1 Link to comment
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