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About atxkyle

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  1. Why do upstream digital components matter
    A novel way to massively improve the SQ of computer audio streaming
    23 hours ago, Speed Racer said:



    15 hours ago, Johnseye said:


    "Clean clock".  Accurate so there's no or minimized distortion.  Low phase noise with an excellent quality clock.

    Yes, the buffer can help but it's not an end all be all and it depends on the DAC.


    I think I've said this before, but it bears repeating from time to time, so people reading this thread are clear about all the confusing clock mods that get tossed around here!


    The whole approach being discussed here with sCLK-EX and reference clocks is NOT ABOUT replacing clocks IN THE DAC! Why? Because most DAC designers - like Ted explains in his video - already take extraordinary care to use high-quality, low-phase-noise clocks in their DACs. It takes an extraordinary clock to improve on this. 


    No - the clock mods being discussed here apply to the usually crappy oscillators found in switches, mobos, Ethernet and USB interfaces, and the like. Replacing these with high-quality, low-phase-noise clocks like the sCLK-EX, and further improved by OCXO reference clocks like the Ref 10, Cybershaft, etc, is what is yielding the SQ improvements so many of us are hearing.


    I also want to be upfront about the fact that we do not really understand why we are hearing these SQ improvements. The SQ improvements undoubtedly exist. Our ears don't lie, and so many here have now heard the benefit. But the fact remains that there is not (yet) a clear scientific explanation for why we are hearing an SQ improvement. This is the usual point of divergence between the subjectivists and the objectivists. The former will accept and enjoy the benefit, while the latter will question whether, absent an explanation, the SQ benefit actually exists.


    I like the approach @JohnSwenson is taking. Rather than being dogmatic, he's digging into the "why" and appears to be making some real headway into understanding what is going on.


    Even though I am a subjectivist, I am not blind to the fact that this is a puzzle. So - what is the puzzle, really? Primarily, it relates to buffers - or buffering. Ted refers to this in the video. Simply put, the question is this: why would the "quality" of an upstream clock matter, when the data being clocked is flowing into a buffer? What is a buffer? In the most abstract sense, it is an area of storage (in this context, in a device's memory) where data is staged before being sent on. In a buffer, data can arrive and leave at different (clock) rates. Think of the buffers involved in a Tidal stream playing through Roon:

    • The stream flows in from your ISP into your modem/router
    • Switches and routers often have buffer memory at each port
    • data flows into the Roon server over the network interface, into a memory buffer in the Roon application, from which it then flows out over the network interface
    • data flows into a streamer (like the sMS-200ultra) over the network interface into a memory buffer in the Roon Ready app, before then flowing out over the USB interface
    • many DACs implement a buffer into which data flows in over USB, say, and is then internally clocked in via the DAC's clock.

    At every such buffer, if the data is received without error, then it is reasonable to ask - why on earth does the phase noise or jitter characteristics of the clock upstream of the buffer have any effect downstream of the buffer? It's a reasonable question, and is ofter the point of contention when people start arguing about this stuff.


    Pending breakthroughs by the people actually digging into this - like John - I only have some conjectures. 


    My strong suspicion is that what we are hearing is the effect of low phase noise clocks on good ol' fashioned analog noise. Let's not think of our long spaghetti chains in terms of their digital functionality, but rather as a connected chain of electronic components, through which analog noise can propagate. Perhaps the impact of low phase noise clocks upstream of the DAC is not in the digital domain, but rather to somehow reduce or mitigate analog noise, either in the data path, the ground plane, or both. Again - this is just a conjecture on my part.


    One of the primary reasons for this conjecture is our other observation of what drives massive SQ improvements in this upstream chain - PSU quality. I've said before that clock quality and PSU quality are independent axes of optimization. We have ample evidence that extreme optimization on either of these axes has a marked effect on SQ.


    I'll leave you with an intriguing thought. Do extreme optimizations on the PSU axis reduce the impact of clock optimizations? Roy's latest findings (over on head-fi) with the Zenith SE suggest this might be a distinct possibility. The Zenith SE does not have any heroic clock optimizations that we know of. What it does have are extreme PSU optimizations. The fact that Roy found it equalled or surpassed his reclocked server - at least in some areas - is highly intriguing. 


    I expect to explore this further soon. But it does underscore the fact that there is much more research and analysis needed to explain why we are hearing these SQ improvements.

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