Reclocking data on SSD hardDrive

[jabbr]

On 12/22/2021 at 7:11 AM, avangerx said:

Hello, I have just seen a new product coming out a stick SSD with a crystek Clock on it. I was wondering are there any benefits of reclocking data on a SSD? 

 

Really no, unless the SSD is total junk in which case it should be replaced. Reclocking the SSD data before it hits the PCI-e bus is sort of ridiculous because it won't reclock the PCIe bus itself. One reason PCIe gen4 has taken so long to get out has been the strict clocking requirements *for the system* including CPU etc. PCIe gen5 is even stricter. If Intel can't meet the spec no little add on is going to fix it.

[jabbr]

On 1/9/2022 at 1:07 AM, yamamoto2002 said:

 

There are total two reference clocks, on both end, per one PCIe interconnect and lower jitter clock on M.2 SSD improves BER of SSD→CPU data transferring path if my understanding is correct. And femtosecond order, not picosecond order of stability is required for PCIe Gen4+ reference clocks. IMO still 70℃ constant temperature oven controlled oscillator is overkill, it is designed to be used for DAC/ADC clock and its frequency stability against ambient temperature change is not necessary for PCIe reference clock (elastic buffer absorbs frequency difference of two reference clocks).

 

Sure, but if the SSD is within spec, and the BER is reasonable, then improving the SSD clock beyond the PCIe receiver clock won't help anything https://pcisig.com/sites/default/files/files/PCI_Express_4_0_Electrical_Previews.pdf -- see discussion of "stressed receiver"

 

Of course this is all measurable.

[jabbr]

1 hour ago, yamamoto2002 said:

SigTest in action

Nice video, everyone should recognize that this was 12 years ago and PCIe gen4 is even tighter/faster than 8 Gbps.

 

The same standard testing is available for Ethernet and all of these tests measure jitter as well as "stressed receiver" which is thge behavior when the incoming signal has maximal allowed jitter.

 

None of the "audiophile" clocking or network device companies seem to provide the results of this testing. In particular I've never seen a shred of evidence that external clocks or clock "upgrades" provide a shred of improvement in system jitter of any kind.

[jabbr]

On 2/16/2022 at 3:38 PM, Dynobot said:

 

Measurable.

 

Everything can be measured....what does it matter if it can not be perceived?

 

Walking past the 'reality' of our perception to focus on an imperceivable measurement is taking a step in the wrong direction. What if we applied the 'religion of measurements' to everything before we consume it....its not realistic.

 

This topic is concerning reclocking data on SSD harddrive ie very technical. *You* don't need to apply the 'religion  of measurements' in order to listen to music, nor do you need to understand the details of a PCIe bus in order to browse the web.

[jabbr]

3 hours ago, Dynobot said:

 

Sooooooo, if you reclock data don't you need to 'measure' jitter to find if the jitter has actually been reduced?

 

I really don't understand what PCIe bus has to do with browsing the web. My computer has one but I don't use it, however I can still browse the web.

 

I'm confused.....this topic is way over my head ie technical....think I'll go to the sideline.

 

😆

 

You are right, the so-called "reclockers" should be measured to see if they do anything. I don't advocate using them and said that it is pointless. There are people who reclock everything and use expensive external clocks  -- which are pointless -- but I've never seen a single end to end measurement to see if these widgets/clocks actually do anything, No I don't do random stuff to my computer and then listen so see if it is "better" because life is short and I use reasonable practices.

 

The relevance of the PCIe bus is that the SSD is connected to it, and right you can browse the web or listen to music without worrying about reclocking the SSD.... that's my point.

[jabbr]

On 6/17/2022 at 2:28 PM, yamamoto2002 said:

 

One possible explanation is, somehow regulated power voltage to DAC chip is fluctuated, DAC clock low-to-hi transition timings are slightly move forward/back in temporal axis, and effectively clock jitter for converting D to A is increased. When it happens, output analog signal will be distorted slightly and it is measured as unwanted peaks of sidelobe on a spectrum analyzer.

 

On a CD player era, local audio magazine explained something like this: when C1 or C2 event occurs on reading the surface pit pattern of CD, extra mechanical action of actuator servo of optical pickup may cause such reference voltage fluctuation.

 

Right and any such voltage fluctuations are isolated across a network. For example the HQPlayer/NAA model puts the drive very far away electrically from the DAC