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"How does the variation in packet delivery alter the performance, when the data itself is undamaged?"

 

The packets are delivered with timing over USB. The timing varies - this is jitter. The timing is used by the receiving device, which must synchronize to this delivery rate in synchronous mode. A local clock is synchronized to the packet rate using a digital phase-locked-loop. The PLL has a loop filter that tries to even out the jitter or speed variations in the delivery rate. The loop filter and the chip doing the PLL is not perfect, so it is somewhat affected by the incoming jitter over USB. Therefore, some of the jitter gets through to the I2S bus on the output of the chip. This varies depending on the implementation and the chip used for the USB to I2S. Devices that use the PCM270X chips are worse than the devices that use the TAS1020 for instance.

 

Steve N.

Empirical Audio

 

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That's fine, but I still don't get how the data payloads are intrinsically altered by timing issues.

 

Perhaps if I explain how I see it in analogy, you can point out where I'm going wrong:

 

Imagine a jigsaw puzzle being sent by UPS, a piece at a time. Every piece is supposed to arrive at midday each day and you have until 1pm on each day to slot that day's piece into the jigsaw. When the UPS guy arrives with the jigsaw piece does not influence how well the piece fits into the jigsaw puzzle, alter the image on the jigsaw piece or change its overall integrity. Of course, if the UPS guy arrives so late that you cannot achieve your 1pm deadline, then the whole jigsaw thing is compromised, but if he arrives a few minutes before or after midday, it makes no difference to the end result.

 

What you seem to be suggesting is that the time the UPS guy arrives does have a profound influence on the jigsaw puzzle. I'm just not convinced its a problem until it becomes a major, jigsaw-breaking problem.

 

vel, Zaphod\'s chust zis guy, you know.

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Steve,

 

My bad. I read up on the USB specs. I was considering the interface in bulk transfer, carefully - but not deliberately - overlooking isochronous transfer. In that light, what you say about jitter propagating over the interface itself makes more sense. I still think it's nowhere near the problem it gets across S/PDIF (with its one line to run both clock and data), but I can see that jitter could manifest between the data packets in principle.

 

vel, Zaphod\'s chust zis guy, you know.

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"Steve, why do you assume that no buffering and re-clocking takes place? The Weiss DACs does this, just as an example."

 

Starcat - Sure, lots of DAC's do PLL reclocking or ASRC, but these are still very jitter sensitive techniques. Even Async USB/Firewire and memory-based reclocking is difficult to make insensitive, and these are theoretically insensitive. My own products and Gordons attempt to make the DAC insensitive and they do get close, but no cigar yet!

 

Maybe my Pace-Car 2 will get there. I have my fingers crossed.

 

Steve N.

 

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Gag - actually virtually all USB interfaces on computers and laptops are extremely jittery compared to a spinning CD disk. The chips that does synchronous adaptive USB protocol has it's work cut-out.

 

The only reason that this USB competes with cd players is the excellent job that TI did on the TAS1020 chip.

 

Steve N.

Empirical Audio

 

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starcat - the main advantage of Firewire is that some will do 24/192, for whatever that's worth. All of the interfaces that I have seen use PLL's, so I dont believe they are asynchronous. Therefore, they are subject to incoming jitter sensitivity. It is possible there is some implementation that I have missed though.

 

BTW, I am looking to license a new USB interface at 24/192 which is async. This requires a custom driver to do 24/192 because the native Windows driver wil not do it.

 

Steve N.

 

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