The Computer Audiophile Posted October 13, 2018 Share Posted October 13, 2018 Hi Guys - I just read this snippet from @John_Atkinson RMAF report. Correct me if I’m wrong or looking at this funny, but it appears that the Verity digital signal processor Pro-6 has the equivalent of a 93 GHz processor in an FPGA. Or, 93 cores at 1 GHz etc... This doesn’t make sense to me given current processor speeds and heat dissipation requirements. Can someone help? JA: “... But the star of the Verity Montsalvat speaker system was the Pro-6, which provides all the DSP correction, crossover functions, and time alignment of the subwoofer towers (these working below 60Hz) with the main speakers. It digitizes analog input signals at 384kHz with 24-bit word length, or accepts USB and S/PDIF digital inputs—PCM and DSD data are handled—and performs all the necessary processing with an FPGA chip capable, I was told, of performing 93 billion operations per second, before converting the resultant drive-unit signal back to analog.” https://www.stereophile.com/content/jas-final-report-rmaf#aroc2USCSrsF4G1I.99 Founder of Audiophile Style | My Audio Systems Link to comment
Popular Post mansr Posted October 13, 2018 Popular Post Share Posted October 13, 2018 All but the most basic FPGAs have hundreds or thousands of DSP blocks that can be connected more or less arbitrarily. Each block typically performs one multiply-accumulate operation per cycle. For example, 200 blocks running at 465 MHz would yield 93 billion operations per second. This figure is about right for a midrange chip. Nothing remarkable. The Computer Audiophile, Thuaveta and ferenc 1 1 1 Link to comment
The Computer Audiophile Posted October 13, 2018 Author Share Posted October 13, 2018 Amazingly helpful answer mans. Thank you. Founder of Audiophile Style | My Audio Systems Link to comment
Popular Post Thuaveta Posted October 14, 2018 Popular Post Share Posted October 14, 2018 7 hours ago, mansr said: All but the most basic FPGAs have hundreds or thousands of DSP blocks that can be connected more or less arbitrarily. Each block typically performs one multiply-accumulate operation per cycle. For example, 200 blocks running at 465 MHz would yield 93 billion operations per second. This figure is about right for a midrange chip. Nothing remarkable. To stress Mans' point on how utterly unremarkable it is, the chip on newer iPhones does 5 trillion operations per second. But, hey, guess you gotta sell 'em million dollar stereos (and impress the old white men helping you doing so)... ferenc and The Computer Audiophile 1 1 Link to comment
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