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Audinate releases Dante IP Core for Xilinx FPGAs


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Dante IP Core

Dante IP Core is a soft IP solution that implements high-performance Dante endpoints on Xilinx FPGA platforms. It enables you to add Dante audio networking flexibly and cost-effectively to FPGA-based AV products, minimizing footprint and reducing BOM expenditures.

Dante IP Core runs efficiently alongside OEM product applications on a range of Xilinx FPGAs, providing channel counts up to 512x512 with ultra-low latency and sub-microsecond synchronization, enabling unprecedented levels of integration and flexibility.

Dante IP Core is the clear choice for manufacturers looking to build best-of-breed Dante solutions with total control over cost, platform, features and performance.

Cost-effective

Get more out of your FPGA expenditures and resources by integrating Dante IP Core alongside your product applications on the same chip. The lower total solution cost of the single-FPGA model returns significant BOM savings that can be used to drive sales, boost margins, or deliver extra features.

Compact

By reducing designs to a single FPGA, products can be built with a smaller footprint and lower total power consumption. ASRC, audio encryption, signal processing modules – your choice of additional functionality can be built directly into the FPGA alongside the Dante core, simplifying your design process and enabling a huge range of unique and disruptive products.

Flexible

Dante IP Core runs on the Xilinx Spartan-6 FPGA family and several 7-series FPGA families, allowing you to choose the optimal part for your product needs, space constraints, and power requirements.

With support for up to 512x512 channels and 128x128 audio flows at sample rates up to 192kHz, Dante IP Core packs the same mighty punch as Audinate’s flagship Dante HC module – and is also available with lower channel-count configurations to enable cost-effective products for all segments of the industry.

Future-proof

Dante IP Core gives you the flexibility to upgrade your design with newer FPGA parts as they become available, allowing you to keep pace with the industry and stay on point with class-leading products that pass even the most demanding performance benchmarks.

Feature-packed

The Dante IP Core solution includes all the interfaces required for a complete and fully-functional Dante endpoint, including network, SiLabs VCXO clock, serial audio, DDR2 or DDR3 and SRAM, plus a variety of standard control interfaces including UART, SPI and I2C.

Segregated from the audio processing engine, system management is handled by an integrated Microblaze soft-core CPU, which supports custom user code for your own embedded Dante API applications.

Responsive Support, Extensive Resources

The Dante IP Core license includes a substantial technical support package, and access to a comprehensive repository of mature development resources to help you design and implement host integration, embedded applications, and remote control and monitoring systems.

Specifications

Audio

  • Sample rates up to 192 kHz in multiples of 44.1/48kHz with pull-up/down
  • Bit depths: 24, 16 and 32 bits per sample
  • Up to 512x512 channels at 44.1/48kHz, 256x256 channels at 88.2/96kHz and 128x128 channels at 176.4 /192kHz
  • Up to 128x128 simultaneous audio packet streams for transmit and receive
  • Up to 1024 samples audio buffering per channel
  • Flexible synchronous serial audio interface, up to 32 x SDIN and 32 x SDOUT audio lines
  • Hardware audio metering

Network

  • Standard RGMII/MII interface for Ethernet PHY or switch chip
  • Software and firmware are upgradable over network

Clock

  • High-quality, low jitter clock with companion Silicon Labs clock generator
  • External word clock sync input

Dante-IP-core-architecture-v2.png

What’s Included

  • Reference Project for ISE / Vivado
    • NGC / encrypted ED IF netlists
    • Top Level example file and constraints
    • Supporting files
  • Build scripts
  • Testbench with encrypted source files (Modelsim)
  • Reference schematics
  • Layout guidelines
  • Reference BOM
  • Activation dongle

Supported Platforms

  • Spartan 6
  • Artix 7 (available Q1 2018)
  • Contact sales for information about additional Xilinx platform support

Download the Dante IP Core Datasheet

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11 hours ago, ferenc said:

 

Clock

  • High-quality, low jitter clock with companion Silicon Labs clock generator
  • External word clock sync input

 

I'm curious what they define as "low jitter", because these are PLL clocks generated from the network packets...

 

Signalyst - Developer of HQPlayer

Pulse & Fidelity - Software Defined Amplifiers

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1 hour ago, Miska said:

 

I'm curious what they define as "low jitter", because these are PLL clocks generated from the network packets...

 

They say they have external word clock sync input as well. 

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This seems to be a smarter solution than the Merging Zman board. Ravenna should offer something similar. The greatest drawback of Dante is the lack of DSD support.

 

Matt

"I want to know why the musicians are on stage, not where". (John Farlowe)

 

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9 hours ago, ferenc said:

They say they have external word clock sync input as well. 

 

Word clock input is very problematic, since it is low frequency system and needs PLL clock generator to create the needed high rate clock. Usually it just worsens jitter performance.

 

Signalyst - Developer of HQPlayer

Pulse & Fidelity - Software Defined Amplifiers

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1 hour ago, ferenc said:

I hope we will learn more of it soon as the next NAMM show is coming so probably there will be more announcements regarding this solution.

 

Another common standard is AVB, which is very common on car IVI systems and such. I have a Motu 8D, but haven't got time to do much testing with it yet. I'll be anyway using it mostly through USB connection, but since it also has ethernet I'll do some testing through that too.

 

I'm also planning to get Motu LP32 which is variant of the same.

 

XMOS has AVB implementation for their processors.

Signalyst - Developer of HQPlayer

Pulse & Fidelity - Software Defined Amplifiers

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On 1/3/2018 at 5:15 PM, Miska said:

 

I'm curious what they define as "low jitter", because these are PLL clocks generated from the network packets...

 

Yes and no — without seeing actual IP model, typically FIFO between network input clock and chip clock. Also not clear if they are using Xilinx Ethernet IP (surely that’s where microblaze comes from) or reimplementing. Xilinx Ethernet IP does FIFO typically. Look nice if you are ok with 192k pcm limit.

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On 1/3/2018 at 7:04 PM, matthias said:

This seems to be a smarter solution than the Merging Zman board. Ravenna should offer something similar. The greatest drawback of Dante is the lack of DSD support.

Those are different products. IP is used with your Xilinx board. Zman includes the board. A Ravenna IP module would be great — agreed

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8 hours ago, Miska said:

 

Another common standard is AVB, which is very common on car IVI systems and such. I have a Motu 8D, but haven't got time to do much testing with it yet. I'll be anyway using it mostly through USB connection, but since it also has ethernet I'll do some testing through that too.

 

I'm also planning to get Motu LP32 which is variant of the same.

 

XMOS has AVB implementation for their processors.

AVB requires dedicated or managed switch to work properly, I installed and designed quite a few system for install and PA systems with AVB, mainly using Presonus products.

 

https://www.presonus.com/products/SW5E

 

Strange, but never got an idea to try AVB devices at home, should have to do it soon :)

 

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4 hours ago, jabbr said:

Those are different products. IP is used with your Xilinx board. Zman includes the board. A Ravenna IP module would be great — agreed

 

As I understand what Merging is communicating, they have a plan to promote Ravenna in the wild and their Ravenna Virtual Sound Card is available for Linux which is not true for Dante. So Dante Core availability should push them toward the same direction. 

 

While it makes sense to develop a 2 channel Dante-AES/SPDIF converter for home audio purposes (its 192k limit could be used through the AES/SPDIF), it makes much less sense in case of Ravenna, which can handle higher bitrate and DSD. So Ravenna is better to be integrated inside. I do not know what is the OEM requirement to get their board, it is probably lot more expensive to get and to implement than getting the Dante Core and its FPGA solution. 

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5 hours ago, ferenc said:

AVB requires dedicated or managed switch to work properly, I installed and designed quite a few system for install and PA systems with AVB, mainly using Presonus products.

 

https://www.presonus.com/products/SW5E

 

Strange, but never got an idea to try AVB devices at home, should have to do it soon :)

 

Thanks for sharing your experiences with AVB. Would you please kindly explain how to determine the roles of listeners versus talkers within an audiophile setup? JCAT NET Card with Intel I350 is only good for listeners while talkers require I210.

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1 hour ago, seeteeyou said:

 

Thanks for sharing your experiences with AVB. Would you please kindly explain how to determine the roles of listeners versus talkers within an audiophile setup? JCAT NET Card with Intel I350 is only good for listeners while talkers require I210.

 

"Listeners versus talkers"? 

 

Is this referring to upstream versus downstream devices? Audiophile humor?


"Don't Believe Everything You Think"

System

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29 minutes ago, mourip said:

"Listeners versus talkers"? 

 

Is this referring to upstream versus downstream devices? Audiophile humor?

 

How Does AVB Work

https://vector.com/portal/medien/cmc/events/Webinars/2015/Vector_Webinar_Audio_Video_Bridging_20150612_EN.pdf#page=11

 

AVB Streams, Channels, Talkers and Listeners

http://xcore.github.io/sw_avb/audio.html

 

Here's the NIC with Windows drivers for 45 euros

 

http://www.react-vite.eu/rv_en/produkte/produkt/S2Konnect/PCI-Express-Desktop-Adapter/N-3010AVB.php

 

The switch costs $120

 

https://www.minidsp.com/products/network-audio/avb-sw

 

$299 for the audio endpoint

 

http://www.xmos.com/buy/boards?product=18334

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2 hours ago, seeteeyou said:

 

Thanks for the education. New terms for me even though I use a Focusrite D16 in my speaker system.

...and light bedtime reading :-)

 

Much appreciated.


"Don't Believe Everything You Think"

System

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10 hours ago, ferenc said:

As I understand what Merging is communicating, they have a plan to promote Ravenna in the wild and their Ravenna Virtual Sound Card is available for Linux which is not true for Dante. So Dante Core availability should push them toward the same direction. 

Dante Core would allow a Spartan-6 based DAC such as PS DirectStream to enable Dante input eg https://forums.xilinx.com/t5/Xcell-Daily-Blog/Audiophiles-swoon-over-DirectStream-DSD-audio-DAC-based-on/ba-p/681296

 

Youd need a Dante Virtual Sound Card.

 

Similarly a Ravenna Core would enable the same functionality in the DAC.

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4 hours ago, jabbr said:

Dante Core would allow a Spartan-6 based DAC such as PS DirectStream to enable Dante input eg https://forums.xilinx.com/t5/Xcell-Daily-Blog/Audiophiles-swoon-over-DirectStream-DSD-audio-DAC-based-on/ba-p/681296

 

Do you think there's free space available in the FPGA for that much extra functionality? I'm quite sure PS DirectStream DSP functionality and Dante both take so much space on the FPGA that they cannot coexist on the same FPGA...

 

But interesting link in itself, that the PS DirectStream uses bunch of cascaded filter sections instead of one single-pass filter...

Signalyst - Developer of HQPlayer

Pulse & Fidelity - Software Defined Amplifiers

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9 hours ago, jabbr said:

The family has between 3.8k and 147K logic cells, so would depend on which chip. 

 

The 7 series FPGAs range up to 2000k cells, and the Ultrascale up to 5,500k cells so ...

 

Spartan is a very small and cheap FPGA, the cheapest one. Ultrascale stuff is not cheap (and consumes quite a bit of power too) -> heat.

 

Someone once asked me what would it take to run HQPlayer algorithms on FPGA and after calculations I ended up pretty much at the biggest and fastest Virtex models and still couldn't be sure if it'll fit and work. After that they weren't interested anymore... :D Such FPGAs cost more than traditional CPU + GPU, and much more costly and difficult to work with.

 

9 hours ago, jabbr said:

The Zynq series include an embedded ARM (dual vs quad core) eliminating the need for the Microblaze CPU. This is what the Merging board uses.

 

I'm more Altera guy... ;)

But I had things running on similar Altera's SoC:

https://www.altera.com/products/soc/overview.html

 

The lightest Cyclone-V SoC is enough for NAA use.

 

9 hours ago, jabbr said:

Perhaps much easier is to run the network stack on the ARM which would enable networkaudiod or a similar protocol, Roon etc. to run the network io, sending buffers to the FPGA -> DSD, PCM or I2S as desired. The FPGA side, for example, can run on an external clock

 

Yes, certainly! Probably that's how Ravenna works too. Those FPGA SoCs are just normal computers with FPGA glue around. Fairly easy to work with and very flexible.

 

Signalyst - Developer of HQPlayer

Pulse & Fidelity - Software Defined Amplifiers

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One of the things, as an example, that you could do on an FPGA would be to alter the phase error in a fine grained fashion as well as instrument the logic so that you could also measure phase error in real-time. You could even build a multi GHz testbench (scope etc) into the FPGA itself — multi GHz using the newer RF SoC — or one of the older ones using Analog Devices add on logic for SDR (software defined radio).

 

I think this newer generation of hybrid CPU/FPGA and it’s increasing adoption is an explicit acknowledgement that certain processing is much better done on CPU and other on FPGA, and you can use both more effectively.

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5 hours ago, jabbr said:

I think this newer generation of hybrid CPU/FPGA and it’s increasing adoption is an explicit acknowledgement that certain processing is much better done on CPU and other on FPGA, and you can use both more effectively.

 

I see FPGA mostly as flexible I/O glue to be used for simple logic level glue. Not really for any processing.

 

If you want to get to CPU-like clock speeds (sample-rate-to-instruction ratio) of about 4.5 GHz, you will end up with the most expensive and power-hungry FPGAs. And still likely won't achieve those clocks speeds. 102040 clock cycles per 44.1 kHz input sample is quite nice margin to have. :)

 

Signalyst - Developer of HQPlayer

Pulse & Fidelity - Software Defined Amplifiers

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1 hour ago, Miska said:

 

I see FPGA mostly as flexible I/O glue to be used for simple logic level glue. Not really for any processing.

 

If you want to get to CPU-like clock speeds (sample-rate-to-instruction ratio) of about 4.5 GHz, you will end up with the most expensive and power-hungry FPGAs. And still likely won't achieve those clocks speeds. 102040 clock cycles per 44.1 kHz input sample is quite nice margin to have. :)

 

Exactly! so putting an Ethernet frame(s) into a buffer — and splitting out the DSD into parallel I/O lines under control of an external clock is very very simple. No need for clocks in the GHz range — Ethernet can go in with a dedicated high speed I/O (eg GTX I think on Altera) — FPGAs used in 100gbe NICs. FPGA makes great IO machine .... math ... err depends.

 

But doing DSD1024 x 16 (saturates 1Gbe) is doable. 

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