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D/A Converter IC's

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Anyone know of any state of the art DAC chips that has a digital buffer (RAM) for the input words? I imagine timing errors due to clock skew would go down drastically, since the conversion clock and memory clock are not only on the same clock tree, but in the same silicon (drift from temperature variations is the same). I guess I could look at some data sheets but i'm being lazy this morning. It seems to me the issue of interface jitter would become irrelevant so long as the other flow control pieces (for instance, between the s/pdif chip and this DAC with internal buffer) are engineered correctly for streaming audio applications. Thoughts?




Squeezebox -> Bel Canto DAC 3 -> XLR -> Audio Research 100.2 -> Dynaudio Contour S3.4

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I had a dpa years ago...


All new chips get their jitter from the Master Clock. Many of these have to have some ram area as they are do digital filtering and such.


For any jitter input device a secondary PLL/VCXO reclocker or FIFO has been used to lower the jitter but all of these act like a low pass filter and can only remove so much.





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The new Naim DAC puts the data from SPDIF in to a FiFO (First In First Out) RAM buffer and then clocks the data out of that via its own master clock to the DAC process. They have a very interesting white paper on how it all works on their web site.




Regards,[br]Steve W[br]http://www.steveww.org/[br]Linux MPD (silent PC) -> MF V-Link II -> Benchmark HDR -> Hypex UcD400 x 2 (mono) -> Heybrook Sextet

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Actually the NAIM units use two powerful Analog Devices DSP's as the buffers, not FIFO's. Their clock is very interesting as with SPDIF or any synchronous protocol requires changing the speed of the Master Clock used for the dac as flow control for the data. To do this they use a standard oscillator with some relays to either up the frequency, make it stay neutral or lower the frequency.


It's a noval idea that I think was tested in the latest Stereophile.





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How the Naim stuff works... is it 10 separate frequencies ( which would be a bit silly ), or a quantized faster/slower circuit?


Every DAC with a built in filter has some RAM ( or the filter wouldn't work... )

No DAC IC has by itself any way of controlling this buffer by handshaking with the source. There are topologies that do, but this is a completely separate issue.

I do object to people saying FIFOs are the greatest thing since sliced bread - they're good things, don't get me wrong, but what other kind of memory/storage would do you any good? (think about it... ) And the Naim spinning memory analogy - there have been loads of products using circular buffers since the 1970s or so - most DSP chips has hardware dedicated to this very purpose, again since 1990 or so...


your friendly neighbourhood idiot


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There is a good shot of the inside of the dac main PCB. Now it could be said that there are two oscillators as you can see two crystals in the oscillator section of the board. I am not sure if they are upsampling and using these as concatenated single oscillator or actually two separate oscillators.


Either way most MCLK frequencies do include many sub frequencies. Like 22.5792 can support 44.1, 88.2, 176.4 and 24.576 can support 32, 48, 96 and 192.


That makes 7.... who know actually.


I have not forgotten your email, I have been swamped and will answer it today.





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