Popular Post jabbr Posted May 31, 2017 Popular Post Share Posted May 31, 2017 @Miska has published an Open Hardware design for a discrete DSD DAC which is easy to understand and serves as an excellent archetypical platform to understand the essence of what a DSD DAC does. http://signalyst.com/hardware.html The schematic [Dsc1.pdf] which defines an electrical circuit is a mathematical description of the circuit. Simulation software such as variations of SPICE e.g. LTSPICE are able to use schematics , and mathematical descriptions of the elements, to simulate circuits. The DSC1 DAC is comprised of three components: 1) the USB interface is an external module whose function is to accept USB and output I2S/DSD. For the purposes of our discussion we will assume the DSD input to the DSC1 as: 1) BCLK — the bit clock 2) DSDR — the right channel bitstream 3) DSDL — the left channel bitstream The USB interface is limited to DSD512 Note that a multichannel DSC1 could be made using additional DSD lines for each channel (same BCLK). The bandwidth of the DSC1 following the USB->DSD stage is limited by the shift registers and so DSD2048 would be possible. (100Mhz BCLK). The DSC1 has two filter stages, the first a digital FIR filter. This is a 32 bit moving average created by 4 x 8 bit shift registers. The DSD signal is clocked in and then the output resistors are summed to produce the output current. This stage produces a simple digital filter which has the effect of creating 32 output lines and thus serving as a simple current amplifier, As a running average, digital noise in the output stage is reduced. Running average FIR filters are well described and their effects well known: http://eeweb.poly.edu/~yao/EE3054/Chap6.1_6.2_L3.pdf http://www.dspguide.com/ch15.htm Following the shift register FIR stage, the remainder of the circuitry is analog. First an I-V conversion stage converting the averaged output current into a voltage. Next comes 2 stages of 2 pole Sallen-Key (SK) Filter, each associated with an OP amp, so a 4 pole SK filter. This is followed by an output buffer. SK Filters are well described: https://en.wikipedia.org/wiki/Sallen–Key_topology http://www.analog.com/media/en/training-seminars/tutorials/MT-222.pdf If we consider the DSD stream linearly (such that it is described by its fourier transform) we have an input signal and through the SDM process, high frequency components are added such that the output signal has binary values and follows the BCLK frequency. These digitizing components can be considered as “error” from the original analogue signal, and from the DAC’s point of view can be considered as “noise” to be removed in the process of reproducing the output signal. (noise from the point of view of the amplifier which follows) As the BCLK gets higher and higher, the “error” or “noise” gets pushed into higher and higher frequencies thus easing the ability of the low pass filter (LPF) in the DAC to reconstruct the original signal. The SDM process involves mathematical operations such that the “carrier” signal which is introduced precisely forms binary values but reversing this process simply involves a LPF. The DSC1 DAC itself does not need, nor has, knowledge of SDM, rather it is an LPF and in particular a 4 pole SK filter which follows a 32 bit running average FIR. A discussion of the DSC1 is here: http://www.diyaudio.com/forums/digital-line-level/254935-signalyst-dsc1.html This is a description of the DSC1 however the PDF is definitive in case this description is not accurate or does not precisely follow the mathematical description as published in the schematic. The intention of this thread is to promote discussion as a way of improving our conceptual understanding of how a DSD DAC works. @Miska may provide more details on the reasoning behind the FIR, among other things louisxiawei, bogi, Solstice380 and 2 others 4 1 Custom room treatments for headphone users. Link to comment
Popular Post Miska Posted May 31, 2017 Popular Post Share Posted May 31, 2017 6 hours ago, jabbr said: The DSC1 has two filter stages, the first a digital FIR filter. This is a 32 bit moving average created by 4 x 8 bit shift registers. The DSD signal is clocked in and then the output resistors are summed to produce the output current. Analog FIR... Since there are 32 elements, there are 33 different possible output levels. The shift registers essentially create a scrambled unary coded value (as opposed to binary coded with PCM), sometimes called "thermometer code". This is how most SDM converters work (for example ESS Sabre, which has 64 elements). Compared to R2R ladder, in this type of converter, accuracy of the resistors don't affect conversion accuracy, only filter's frequency response. Every bit goes through every element once and every bit is converted 32 times. Since every new sample has only 1/32th contribution to the converted value, it has filtering effect and thus reduces the slew rate I/V section is seeing which makes it easier to create good I/V and analog filter stages - lower level high frequency content. So the maximum sample-to-sample voltage step after I/V is 1/32th of the full range. Using equal weighting for each element provides best possible jitter rejection but less filtering effect. semente, Jud, bogi and 1 other 4 Signalyst - Developer of HQPlayer Pulse & Fidelity - Software Defined Amplifiers Link to comment
jabbr Posted May 31, 2017 Author Share Posted May 31, 2017 3 hours ago, Miska said: Analog FIR... Since there are 32 elements, there are 33 different possible output levels. The shift registers essentially create a scrambled unary coded value (as opposed to binary coded with PCM), sometimes called "thermometer code". This is how most SDM converters work (for example ESS Sabre, which has 64 elements). Compared to R2R ladder, in this type of converter, accuracy of the resistors don't affect conversion accuracy, only filter's frequency response. Every bit goes through every element once and every bit is converted 32 times. Since every new sample has only 1/32th contribution to the converted value, it has filtering effect and thus reduces the slew rate I/V section is seeing which makes it easier to create good I/V and analog filter stages - lower level high frequency content. So the maximum sample-to-sample voltage step after I/V is 1/32th of the full range. Using equal weighting for each element provides best possible jitter rejection but less filtering effect. Hybrid In this FIR design, the "thermometer code" would often be followed by a summation block to convert to binary (PCM encoding) if one wanted to keep this in the digital domain (and minimize bit width) The exact point of D/A conversion occurs when the 32 lines which carry the digital average (thermometer encoded) are summed using the resistor network and become analog current. So perhaps we don't need to use RF jFets in the I-V converter after all SPICE simulation suggests that bandwidth limitation occurs as a result of the input capacitance of the jFet. By using parallel jFets we can keep within the linear current range (improving distortion) and reduce noise, and by cascoding, reduce the effective input capacitance. A disadvantage of using RF jFets is that they can tend to oscillate if the layout is careful etc. -- kind of like the accelerator on a Ferrari The advantage of a discrete I-V would be that very specific circuit parameters can be tweaked. Custom room treatments for headphone users. Link to comment
Miska Posted May 31, 2017 Share Posted May 31, 2017 10 hours ago, jabbr said: In this FIR design, the "thermometer code" would often be followed by a summation block to convert to binary (PCM encoding) This scrambled unary coding has many advantages over binary coding and that is the reason why it is so much used these days in converters. It also means that you need to deal with low number of levels. Creating even 16-bit PCM DAC using similar technique would be pretty impractical, although theoretically possible! Signalyst - Developer of HQPlayer Pulse & Fidelity - Software Defined Amplifiers Link to comment
Jud Posted May 31, 2017 Share Posted May 31, 2017 Was hoping you'd start this thread - thanks! Middy 1 One never knows, do one? - Fats Waller The fairest thing we can experience is the mysterious. It is the fundamental emotion which stands at the cradle of true art and true science. - Einstein Computer, Audirvana -> optical Ethernet to Fitlet3 -> Fibbr Alpha Optical USB -> iFi NEO iDSD DAC -> Apollon Audio 1ET400A Mini (Purifi based) -> Vandersteen 3A Signature. Link to comment
jabbr Posted May 31, 2017 Author Share Posted May 31, 2017 An interesting question will be whether DSD1024 will be better, worse, or the same as DSD512 after upsampling. At some point the increased close-in phase error of the 45 Mhz clock, being worse (laws of physics) than an equivalent 22 Mhz clock will increase noise rather than improve. I had predicted that DSD512 would be equivalent to DSD256 for this reason but many people hear DSD512 as being better (the problem is, however, that you need to use different clocks, and not simply compare DSD256 vs DSD512 on the same DAC because its the master clock that determines, not the clock that is derived by division. Custom room treatments for headphone users. Link to comment
mansr Posted May 31, 2017 Share Posted May 31, 2017 33 minutes ago, Miska said: This scrambled unary coding has many advantages over binary coding and that is the reason why it is so much used these days in converters. Dynamic element matching is another name for this. Link to comment
Miska Posted May 31, 2017 Share Posted May 31, 2017 5 minutes ago, jabbr said: An interesting question will be whether DSD1024 will be better, worse, or the same as DSD512 after upsampling. At some point the increased close-in phase error of the 45 Mhz clock, being worse (laws of physics) than an equivalent 22 Mhz clock will increase noise rather than improve. I had predicted that DSD512 would be equivalent to DSD256 for this reason but many people hear DSD512 as being better (the problem is, however, that you need to use different clocks, and not simply compare DSD256 vs DSD512 on the same DAC because its the master clock that determines, not the clock that is derived by division. From objective point of view, the improvement with DSD512 on DACs like DSC1 or T+A DAC8 DSD is that the amount of ultrasonic noise passing through gets reduced quite significantly. At DSD512, DSC1 gives practically flat noise floor. From audio bandwidth point of view, DSD512 should be already enough, and those 22/24 MHz clocks have pretty good phase noise performance, at least compared to 100 MHz clocks typically used with ESS Sabre... Signalyst - Developer of HQPlayer Pulse & Fidelity - Software Defined Amplifiers Link to comment
Miska Posted May 31, 2017 Share Posted May 31, 2017 3 minutes ago, mansr said: Dynamic element matching is another name for this. Yes, sure. ESS Sabre calls their DEM "Revolver" because it's a barrel rotator. But even without considering the conversion element part, it has advantages in digital domain. Scrambled unary presentation can have multiple representations for the same value, while binary has only one. For example binary: 01 -> value 1 10 -> value 2 Same in scrambled unary: 0001 -> value 1 0010 -> value 1 0100 -> value 1 1000 -> value 1 1001 -> value 2 0110 -> value 2 1010 -> value 2 0101 -> value 2 1100 -> value 2 0011 -> value 2 Signalyst - Developer of HQPlayer Pulse & Fidelity - Software Defined Amplifiers Link to comment
mansr Posted May 31, 2017 Share Posted May 31, 2017 6 minutes ago, Miska said: Yes, sure. ESS Sabre calls their DEM "Revolver" because it's a barrel rotator. I'm going to make a Gatling DAC. Link to comment
jtwrace Posted May 31, 2017 Share Posted May 31, 2017 49 minutes ago, Miska said: From objective point of view, the improvement with DSD512 on DACs like DSC1 or T+A DAC8 DSD is that the amount of ultrasonic noise passing through gets reduced quite significantly. At DSD512, DSC1 gives practically flat noise floor. From audio bandwidth point of view, DSD512 should be already enough, and those 22/24 MHz clocks have pretty good phase noise performance, at least compared to 100 MHz clocks typically used with ESS Sabre... Is there still any advantage of using your dac with Roon but not HQP? W10 NUC i7 (Gen 10) > Roon (Audiolense FIR) > Motu UltraLite mk5 > (4) Hypex NCore NC502MP > JBL M2 Master Reference +4 subs Watch my Podcast https://www.youtube.com/channel/UCXMw_bZWBMtRWNJQfTJ38kA/videos Link to comment
Miska Posted May 31, 2017 Share Posted May 31, 2017 14 minutes ago, jtwrace said: Is there still any advantage of using your dac with Roon but not HQP? You can use it with anything that can spit out DSD, as long as you use at least DSD128. Don't try to run it at DSD64, you'd get poor results. Signalyst - Developer of HQPlayer Pulse & Fidelity - Software Defined Amplifiers Link to comment
jtwrace Posted May 31, 2017 Share Posted May 31, 2017 Just now, Miska said: You can use it with anything that can spit out DSD, as long as you use at least DSD128. Don't try to run it at DSD64, you'd get poor results. Is there a simple PDF of what's required to DIY it? Do you sell assembled boards for the lazy? Measurements? W10 NUC i7 (Gen 10) > Roon (Audiolense FIR) > Motu UltraLite mk5 > (4) Hypex NCore NC502MP > JBL M2 Master Reference +4 subs Watch my Podcast https://www.youtube.com/channel/UCXMw_bZWBMtRWNJQfTJ38kA/videos Link to comment
Jud Posted June 1, 2017 Share Posted June 1, 2017 26 minutes ago, jtwrace said: Is there a simple PDF of what's required to DIY it? Do you sell assembled boards for the lazy? Measurements? Re the first two, schematics and no. I'll leave the last to someone who knows. One never knows, do one? - Fats Waller The fairest thing we can experience is the mysterious. It is the fundamental emotion which stands at the cradle of true art and true science. - Einstein Computer, Audirvana -> optical Ethernet to Fitlet3 -> Fibbr Alpha Optical USB -> iFi NEO iDSD DAC -> Apollon Audio 1ET400A Mini (Purifi based) -> Vandersteen 3A Signature. Link to comment
bibo01 Posted June 1, 2017 Share Posted June 1, 2017 Re. measurements, Miska published some in his blog: https://www.computeraudiophile.com/blogs/blog/83-miskas-blog/ How curious are you? Link to comment
jabbr Posted June 1, 2017 Author Share Posted June 1, 2017 13 hours ago, Miska said: Yes, sure. ESS Sabre calls their DEM "Revolver" because it's a barrel rotator. But even without considering the conversion element part, it has advantages in digital domain. Scrambled unary presentation can have multiple representations for the same value, while binary has only one. For example binary: 01 -> value 1 10 -> value 2 Same in scrambled unary: 0001 -> value 1 0010 -> value 1 0100 -> value 1 1000 -> value 1 1001 -> value 2 0110 -> value 2 1010 -> value 2 0101 -> value 2 1100 -> value 2 0011 -> value 2 My (admittedly limited) understanding of DEM is that these multiple representations can be used to map depending on say a resistor value which may vary, and again for example, with an R2R ladder with more bits than appropriate for the accuracy level of the resistors, and in which non-monotonic transitions can occur, than DEM can be used to linearize or improve the accuracy of the R2R by selecting certain of the scrambled codes. (mapping the scrambled codes in order to linearize) In the DSC1, is it correct that this is not needed? Because the running average always averages across the 32 resistors? ... otherwise, oh well I guess 32 bit LUTS are possible ... are you waiting for dual ported BRAM prices to come down for DSC2? Custom room treatments for headphone users. Link to comment
jabbr Posted June 1, 2017 Author Share Posted June 1, 2017 Perhaps another use for DEM would be in a balanced DSC1 to linearize differences in the analogue electronics on the (+) and (-) sides. Probably easier to use trimmer pots Custom room treatments for headphone users. Link to comment
shadowlight Posted June 1, 2017 Share Posted June 1, 2017 14 hours ago, jtwrace said: Is there a simple PDF of what's required to DIY it? Do you sell assembled boards for the lazy? Measurements? If you search ebay for DSC1 you will find couple of users selling assembled boards. Link to comment
Jud Posted June 1, 2017 Share Posted June 1, 2017 Just now, shadowlight said: If you search ebay for DSC1 you will find couple of users selling assembled boards. Yes, but it's quite difficult to tell what those actually are. One never knows, do one? - Fats Waller The fairest thing we can experience is the mysterious. It is the fundamental emotion which stands at the cradle of true art and true science. - Einstein Computer, Audirvana -> optical Ethernet to Fitlet3 -> Fibbr Alpha Optical USB -> iFi NEO iDSD DAC -> Apollon Audio 1ET400A Mini (Purifi based) -> Vandersteen 3A Signature. Link to comment
jabbr Posted June 1, 2017 Author Share Posted June 1, 2017 2 hours ago, Jud said: Yes, but it's quite difficult to tell what those actually are. They look like they have output transformers Custom room treatments for headphone users. Link to comment
4est Posted June 1, 2017 Share Posted June 1, 2017 4 hours ago, jabbr said: They look like they have output transformers There are two versions and different kits- soldered, un soldered ect. One version akin to the original, and a second balanced version- kits with 1:1 transformers and sans transformers. I soldered mine and use my TVC as the transformer. It works great! Forrest: Win10 i9 9900KS/GTX1060 HQPlayer4>Win10 NAA DSD>Pavel's DSC2.6>Bent Audio TAP> Parasound JC1>"Naked" Quad ESL63/Tannoy PS350B subs<100Hz Link to comment
jabbr Posted June 1, 2017 Author Share Posted June 1, 2017 Care to post a schematic? Custom room treatments for headphone users. Link to comment
4est Posted June 1, 2017 Share Posted June 1, 2017 1 minute ago, jabbr said: Care to post a schematic? What schematic? I bought mine bare board with labeled parts before there were assembled ones available. It was only about $50 with everything but transformers and I gave it a shot. No regrets. I question the inexpensive transformers, you don't get much for $20. The rest of it is solid, subjectively functioning pretty well. You asked before about the circuit, but there is no schematic for the balanced one. Those parts are minuscule and a lil different than Miska's choices. I have a better scope now, and maybe I can read them. Let me know and I'll take a look. Forrest: Win10 i9 9900KS/GTX1060 HQPlayer4>Win10 NAA DSD>Pavel's DSC2.6>Bent Audio TAP> Parasound JC1>"Naked" Quad ESL63/Tannoy PS350B subs<100Hz Link to comment
bibo01 Posted June 2, 2017 Share Posted June 2, 2017 @Miska Will a DSC2 ever see the light? That device I was telling you about in PM would be the perfect candidate to go with it. MrMoM 1 How curious are you? Link to comment
jabbr Posted June 2, 2017 Author Share Posted June 2, 2017 16 hours ago, 4est said: What schematic? I bought mine bare board with labeled parts before there were assembled ones available. It was only about $50 with everything but transformers and I gave it a shot. No regrets. I question the inexpensive transformers, you don't get much for $20. The rest of it is solid, subjectively functioning pretty well. You asked before about the circuit, but there is no schematic for the balanced one. Those parts are minuscule and a lil different than Miska's choices. I have a better scope now, and maybe I can read them. Let me know and I'll take a look. Ok I thought perhaps they gave a bill of materials and schematic so you'd know what you were soldering where. Balancing a single bit SDM stream is easy using a D-Flop which outputs + and -. Regarding digital switching noise, if both sides have very precise phase, then theoretically the switching signals will cancel. Changes in current will balance eachother. One issue, however, is when the signals arrive at different times to the chips. This can be caused by unequal trace path lengths and impedances. PCB routing can be important in this situation. Does this make a difference? Well we talk about so-called "femtosecond" clocks. Signals travel down a one foot PCB trace in 1 - 2 nanoseconds -- so if the trace lengths are unequal that's a lot of femtoseconds Vias also insert uncertainty. Another issue is clock distribution -- when a trace is fanned out this causes reflections (and phase error). A clock distribution chip reduces that (along with trace termination). I've thought it amusing that many folks get caught up with using the latest and greatest "femtosecond" or "atomic" clock without a care in the world about how the DAC circuit actually works... now I'd be fairly certain that vendors such as ESS (and any large chip manufacturer) spend a fair amount of resources modeling trace delay and fan-out etc. -- particularly when they work at 100Mhz. For Ghz applications its absolutely essential. Anyways when I think about folks "upgrading" a cheap circuit with an unknown design by using the worlds greatest and most accurate clock -- which costs waay more than the circuit its being applied to, my brain goes into a fog... Custom room treatments for headphone users. Link to comment
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