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The DSC1 DAC as a way to understand how a simple DSD DAC actually works


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10 hours ago, jabbr said:

In this FIR design, the "thermometer code" would often be followed by a summation block to convert to binary (PCM encoding)

 

This scrambled unary coding has many advantages over binary coding and that is the reason why it is so much used these days in converters. It also means that you need to deal with low number of levels. Creating even 16-bit PCM DAC using similar technique would be pretty impractical, although theoretically possible! :D

 

Signalyst - Developer of HQPlayer

Pulse & Fidelity - Software Defined Amplifiers

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5 minutes ago, jabbr said:

An interesting question will be whether DSD1024 will be better, worse, or the same as DSD512 after upsampling. At some point the increased close-in phase error of the 45 Mhz clock, being worse (laws of physics) than an equivalent 22 Mhz clock will increase noise rather than improve.

 

I had predicted that DSD512 would be equivalent to DSD256 for this reason but many people hear DSD512 as being better (the problem is, however, that you need to use different clocks, and not simply compare DSD256 vs DSD512 on the same DAC because its the master clock that determines, not the clock that is derived by division.

 

From objective point of view, the improvement with DSD512 on DACs like DSC1 or T+A DAC8 DSD is that the amount of ultrasonic noise passing through gets reduced quite significantly. At DSD512, DSC1 gives practically flat noise floor. From audio bandwidth point of view, DSD512 should be already enough, and those 22/24 MHz clocks have pretty good phase noise performance, at least compared to 100 MHz clocks typically used with ESS Sabre...

 

Signalyst - Developer of HQPlayer

Pulse & Fidelity - Software Defined Amplifiers

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3 minutes ago, mansr said:

Dynamic element matching is another name for this.

 

Yes, sure. ESS Sabre calls their DEM "Revolver" because it's a barrel rotator.

 

But even without considering the conversion element part, it has advantages in digital domain. Scrambled unary presentation can have multiple representations for the same value, while binary has only one.

 

For example binary:

01 -> value 1

10 -> value 2

 

Same in scrambled unary:

0001 -> value 1

0010 -> value 1

0100 -> value 1

1000 -> value 1

1001 -> value 2

0110 -> value 2

1010 -> value 2

0101 -> value 2

1100 -> value 2

0011 -> value 2

 

Signalyst - Developer of HQPlayer

Pulse & Fidelity - Software Defined Amplifiers

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  • 3 weeks later...
6 hours ago, Eclectico said:

In other points, what is the accuracy of the sine wave in the output of DSC1 dac in comparaison to 16 bits dac?

Output is 32 possible voltage levels against 65536 for 16 bits DAC...

What think about that?:(

 

L0108_BitGraph.png

 

One error with those graphs is that they are in completely wrong time scale, lower bit depths would have much finer time steps. You are now comparing PCM and SDM DACs by just looking at "bits" which is not going to help at all. Two completely different things.

 

Overall, there are various different aspects to this...

 

1) In PCM ladder, each bit is weighted by 2^x where x is number of the bit towards MSB. In SDM array, each bit is typically equally weighted. This helps a lot because accuracy of resistors become much less important, in fact for DSC1 type it doesn't matter much and doesn't change linearity of the DAC at all.

2) With PCM ladder, more bits you have, lower the sampling rate needs to be in order for the levels to be able to settle within ½LSB precision in fraction of the sample time (0.1%, IOW in 1/1000th of the sample time is good measure). Otherwise the bits become useless.

3) Lower the sampling rate, more challenging the following analog reconstruction filter becomes, because for perfect reconstruction, the first image and everything above that needs to be removed completely. Images are of course directly correlated with the source signal, so they also cause directly correlated distortion products.

4) SDM has just increasing ultrasonic random noise slope, any distortion products would be decorrelated from the source signal.

 

Since DSC1 can crank out any of the 33 possible voltage levels at 24.576 MHz speed, that is new level every 40 nanoseconds, this gives a lot of room for noise shaping to operate.

 

While typical PCM ladder DAC runs up to 384 kHz speed, being able to produce new level every 2.6 microseconds.

 

Signalyst - Developer of HQPlayer

Pulse & Fidelity - Software Defined Amplifiers

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6 hours ago, louisxiawei said:

My friend who is DIY DSC1 himself has a problem regarding using Amerano firmware in the DSC1.  He is currently using Amanero firmware 1096c and CPLD version 1080 , this combo playbacks music signal (DSD512) well but has some pop sound issue when switching PCM signal to DSD one. 

 

Well, the DSC1 doesn't play PCM at all... But this depends on the MUTE signal handling of the Amanero.

 

6 hours ago, louisxiawei said:

Now he is testing Amanero 1099c1 and CPLD 1080, although there is no pop-sound when switching PCM signal to DSD, it has another pulse noise when playback DSD512 signal.

 

This is a known issue, 1099 firmware versions don't work reliably at DSD512 speeds yet. DSD256 tends to work...

Signalyst - Developer of HQPlayer

Pulse & Fidelity - Software Defined Amplifiers

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  • 9 months later...
14 hours ago, HallmanLabs said:

I have two 100uf Rubycon Black Gate capacitors (non-polar version). Do you all think it would be a waste to put them in place of the two 100uF caps seen on the input end of the DSC1 board? Are those two coupling caps in that position? 

 

All electrolytic caps are polarized power supply filtering capacitors. There are two DC block capacitors on the signal path, by default those are 1µF polypropylene ones (big green blocks on my photo).

 

Signalyst - Developer of HQPlayer

Pulse & Fidelity - Software Defined Amplifiers

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