The DSC1 DAC as a way to understand how a simple DSD DAC actually works

[jabbr]

 

 

@Miska has published an Open Hardware design for a discrete DSD DAC which is easy to understand and serves as an excellent archetypical platform to understand the essence of what a DSD DAC does. http://signalyst.com/hardware.html

 

The schematic [Dsc1.pdf] which defines an electrical circuit is a mathematical description of the circuit. Simulation software such as variations of SPICE e.g. LTSPICE are able to use schematics , and mathematical descriptions of the elements, to simulate circuits.

 

The DSC1 DAC is comprised of three components:

 

1) the USB interface is an external module whose function is to accept USB and output I2S/DSD. For the purposes of our discussion we will assume the DSD input to the DSC1 as:

 

1) BCLK — the bit clock

2) DSDR — the right channel bitstream

3) DSDL — the left channel bitstream

 

The USB interface is limited to DSD512

 

Note that a multichannel DSC1 could be made using additional DSD lines for each channel (same BCLK).

The bandwidth of the DSC1 following the USB->DSD stage is limited by the shift registers and so DSD2048 would be possible. (100Mhz BCLK).

 

The DSC1 has two filter stages, the first a digital FIR filter. This is a 32 bit moving average created by 4 x 8 bit shift registers. The DSD signal is clocked in and then the output resistors are summed to produce the output current.

 

This stage produces a simple digital filter which has the effect of creating 32 output lines and thus serving as a simple current amplifier, As a running average, digital noise in the output stage is reduced.

 

Running average FIR filters are well described and their effects well known:

http://eeweb.poly.edu/~yao/EE3054/Chap6.1_6.2_L3.pdf

http://www.dspguide.com/ch15.htm

 

Following the shift register FIR stage, the remainder of the circuitry is analog. First an I-V conversion stage converting the averaged output current into a voltage. Next comes 2 stages of 2 pole Sallen-Key (SK) Filter, each associated with an OP amp, so a 4 pole SK filter. This is followed by an output buffer.

 

SK Filters are well described:

https://en.wikipedia.org/wiki/Sallen–Key_topology

http://www.analog.com/media/en/training-seminars/tutorials/MT-222.pdf

 

If we consider the DSD stream linearly (such that it is described by its fourier transform) we have an input signal and through the SDM process, high frequency components are added such that the output signal has binary values and follows the BCLK frequency. These digitizing components can be considered as “error” from the original analogue signal, and from the DAC’s point of view can be considered as “noise” to be removed in the process of reproducing the output signal. (noise from the point of view of the amplifier which follows)

 

As the BCLK gets higher and higher, the “error” or “noise” gets pushed into higher and higher frequencies thus easing the ability of the low pass filter (LPF) in the DAC to reconstruct the original signal. The SDM process involves mathematical operations such that the “carrier” signal which is introduced precisely forms binary values but reversing this process simply involves a LPF. The DSC1 DAC itself does not need, nor has,  knowledge of SDM, rather it is an LPF and in particular a 4 pole SK filter which follows a 32 bit running average FIR.

 

A discussion of the DSC1 is here: http://www.diyaudio.com/forums/digital-line-level/254935-signalyst-dsc1.html

 

This is a description of the DSC1 however the PDF is definitive in case this description is not accurate or does not precisely follow the mathematical description as published in the schematic. The intention of this thread is to promote discussion as a way of improving our conceptual understanding of how a DSD DAC works.

 

@Miska may provide more details on the reasoning behind the FIR, among other things  

[jabbr]

3 hours ago, Miska said:

 

Analog FIR...

 

Since there are 32 elements, there are 33 different possible output levels. The shift registers essentially create a scrambled unary coded value (as opposed to binary coded with PCM), sometimes called "thermometer code". This is how most SDM converters work (for example ESS Sabre, which has 64 elements). Compared to R2R ladder, in this type of converter, accuracy of the resistors don't affect conversion accuracy, only filter's frequency response. Every bit goes through every element once and every bit is converted 32 times.

 

Since every new sample has only 1/32th contribution to the converted value, it has filtering effect and thus reduces the slew rate I/V section is seeing which makes it easier to create good I/V and analog filter stages - lower level high frequency content. So the maximum sample-to-sample voltage step after I/V is 1/32th of the full range.

 

Using equal weighting for each element provides best possible jitter rejection but less filtering effect.

 

Hybrid  

 

In this FIR design, the "thermometer code" would often be followed by a summation block to convert to binary (PCM encoding) if one wanted to keep this in the digital domain (and minimize bit width) The exact point of D/A conversion occurs when the 32 lines which carry the digital average (thermometer encoded) are summed using the resistor network and become analog current.

 

So perhaps we don't need to use RF jFets in the I-V converter after all  SPICE simulation suggests that bandwidth limitation occurs as a result of the input capacitance of the jFet. By using parallel jFets we can keep within the linear current range (improving distortion) and reduce noise, and by cascoding, reduce the effective input capacitance. A disadvantage of using RF jFets is that they can tend to oscillate if the layout is careful etc. -- kind of like the accelerator on a Ferrari  

 

The advantage of a discrete I-V would be that very specific circuit parameters can be tweaked.

 

[jabbr]

An interesting question will be whether DSD1024 will be better, worse, or the same as DSD512 after upsampling. At some point the increased close-in phase error of the 45 Mhz clock, being worse (laws of physics) than an equivalent 22 Mhz clock will increase noise rather than improve.

 

I had predicted that DSD512 would be equivalent to DSD256 for this reason but many people hear DSD512 as being better (the problem is, however, that you need to use different clocks, and not simply compare DSD256 vs DSD512 on the same DAC because its the master clock that determines, not the clock that is derived by division.

[jabbr]

13 hours ago, Miska said:

 

Yes, sure. ESS Sabre calls their DEM "Revolver" because it's a barrel rotator.

 

But even without considering the conversion element part, it has advantages in digital domain. Scrambled unary presentation can have multiple representations for the same value, while binary has only one.

 

For example binary:

01 -> value 1

10 -> value 2

 

Same in scrambled unary:

0001 -> value 1

0010 -> value 1

0100 -> value 1

1000 -> value 1

1001 -> value 2

0110 -> value 2

1010 -> value 2

0101 -> value 2

1100 -> value 2

0011 -> value 2

 

 

My (admittedly limited) understanding of DEM is that these multiple representations can be used to map depending on say a resistor value which may vary, and again for example, with an R2R ladder with more bits than appropriate for the accuracy level of the resistors, and in which non-monotonic transitions can occur, than DEM can be used to linearize or improve the accuracy of the R2R by selecting certain of the scrambled codes. (mapping the scrambled codes in order to linearize)

 

In the DSC1, is it correct that this is not needed? Because the running average always averages across the 32 resistors? ... otherwise, oh well I guess 32 bit LUTS are possible ... are you waiting for dual ported BRAM prices to come down for DSC2? 

 

[jabbr]

Perhaps another use for DEM would be in a balanced DSC1 to linearize differences in the analogue electronics on the (+) and (-) sides. Probably easier to use trimmer pots

 

[jabbr]

2 hours ago, Jud said:

 

Yes, but it's quite difficult to tell what those actually are.

They look like they have output transformers  

[jabbr]

Care to post a schematic?

[jabbr]

16 hours ago, 4est said:

What schematic?    I bought mine bare board with labeled parts before there were assembled ones available. It was only about $50 with everything but transformers and I gave it a shot. No regrets. I question the inexpensive transformers, you don't get much for $20. The rest of it is solid, subjectively functioning pretty well.

 

You asked before about the circuit, but there is no schematic for the balanced one. Those parts are minuscule and a lil different than Miska's choices. I have a better scope now, and maybe I can read them. Let me know and I'll take a look.

 

Ok I thought perhaps they gave a bill of materials and schematic so you'd know what you were soldering where.

 

Balancing a single bit SDM stream is easy using a D-Flop which outputs + and -. Regarding digital switching noise, if both sides have very precise phase, then theoretically the switching signals will cancel. Changes in current will balance eachother. One issue, however, is when the signals arrive at different times to the chips. This can be caused by unequal trace path lengths and impedances. PCB routing can be important in this situation.

 

Does this make a difference? Well we talk about so-called "femtosecond" clocks. Signals travel down a one foot PCB trace in 1 - 2 nanoseconds -- so if the trace lengths are unequal that's a lot of femtoseconds  Vias also insert uncertainty. Another issue is clock distribution -- when a trace is fanned out this causes reflections (and phase error). A clock distribution chip reduces that (along with trace termination).

 

I've thought it amusing that many folks get caught up with using the latest and greatest "femtosecond" or "atomic" clock without a care in the world about how the DAC circuit actually works... now I'd be fairly certain that vendors such as ESS (and any large chip manufacturer) spend a fair amount of resources modeling trace delay and fan-out etc. -- particularly when they work at 100Mhz. For Ghz applications its absolutely essential.

 

Anyways when I think about folks "upgrading" a cheap circuit with an unknown design by using the worlds greatest and most accurate clock -- which costs waay more than the circuit its being applied to, my brain goes into a fog...

[jabbr]

3 hours ago, Jud said:

By the way, so as not to confuse folks, the references to no schematics were to the Chinese boards - @Miska has schematics and a bill of materials on the Signalyst site.  (@jabbr , I'm sure you have schematics for your version at DIYAudio.  BOM as well?)

Everything is on the DIYAudio site ... the desire to use even more discrete implementations means moving more to SMD components -- the through the hole jFets are an increasingly rare ... and expensive ... breed. SMD components are super cheap in contrast, though soldering them requires skill and is aided by equipment like a stereomicroscope. So maybe not for everyone though several people are working on it. That said, SMD is great for production -- there is typically a substantial setup fee needed to load the rolls of the specific parts but then the production is automated with pick-and-place and then wave solder -- like pizza  

[jabbr]

4 hours ago, 4est said:

I do my best not to think much about what others do.

 

And of course you are correct about the clocking - and the D Flop. That can readily be done on the original board as well, and by using a pair of boards stacked or sandwiched you have stereo. I realize it is sub optimal, but I haven't your expertise and muddle along the DIY trail the best I can with the limited resources available here...

 

People are free to implement any suggested optimizations in any way they see fit. The prices for the Chinese boards are unbeatable and if they would simply publish their schematic I'd be all in favor... I'm not intending to criticize (don't know enough in any case), rather trying to discuss methods we can use to optimize the DSC1 design. That's why its an open design, so we can optimize and discuss the value of optimizations -- and at points where there are rough consensus, then folks might implement -- and at some point a wider board production could be considered. Its hard to know how much actual interest there would be.

[jabbr]

Just curious, what makes this the "perfect situation" for transformers? I 'd love to know the general schematic of the Lampizator. I'd guess a tube filter, but tube I-V?

 

In any case folks like @Superdad or @vortecjr are probably much much more expert than me at getting a good run of boards built  

[jabbr]

1 hour ago, Marco said:

I have no idea of jabbr his boards, but to give an idea of what producing a 2-layer DDC1 board means financially, this might help.

jabbr has a number of variations of boards . Link to purchase at OSH park are on DIYAudio. They require minimum of three but one is needed for each channel, so you'd have one extra to mess up. There are separate boards for the digital section and the analogue section.

 

The digital boards are 4 layered with a proper ground and power plane. The only impediment to mass production is the use of Potato Semi logic for the d-flop and clock distribution. (I'm sure that could be worked out) .

 

The digital board uses standard design techniques.

 

The analogue board is mirrored & balanced (2 layered). It's circuits are less typical -- the I-V section (based on EUVL's SEN which itself is based in Pass' ZEN) is designed as very low noise with parallel (3) jfet & cascoded (total of 12 jfets). The design minimizes current noise. The  op amps are discrete Scott Wurcer hybrid jfet/bjt -- so entirely open design and an ode to the BJ862  -- it will have a unique sound hopefully a great one ☝️ 

[jabbr]

Ah ok. The transformer is being used in lieu of the active output SK filter.

 

One of the reasons to separate the digital and analogue boards are to allow different analogue circuitry.

 

I had simply replaced the opamps in @Miska's original DSC1 design with discrete jFet versions -- in the case of the opamp serving as an I-V converter, with a discrete jfet I-V converter for the reason that we are dealing with current and the jfet has low current noise (which is itself diminished by using 3 parallel devices).

 

The opamps that form the SK filter have been replaced with a discrete hybrid jfet/bjt opamp design. There are other discrete designs, some that have less devices. That particular design was the primary work of Scott Wurcer (who designed opamps for AD) along with the input of some other luminaries and being itself a freely available DIYA design, I wanted to incorporate it into DSC1.2. To be very clear, there are other discrete designs that could be used, maintaining the same Sallen-Key filter characteristics that are used in the DSC1.

 

Now if the Chinese "DSC1" is transformer based, then the question arises: What makes it "DSC1" and what characteristics does it share with the Signalyst DSC1?

[jabbr]

2 hours ago, 4est said:

At dsd512 there is little noise near the audio band, and the transformers filter that while also providing a true balanced signal and galvanic isolation -all with one part. In contrast, I've seen some of your designs on DIYAudio - a dozen active devices, two power supplies and a dozen or two resisters/caps per channel. That is a lot of stuff. Transformers have limitations, but an active circuit would have to be very well tuned to compete sonically.

Let me expand on this -- and give a listening impression.

 

I have both a FirstWatt M2 which is transformer based as well as the J2 which is JFET based. Although the M2 is terrific, the J2 is phenomenal.

 

The original DSC1 sounds really excellent. I am looking for the J2 level of phenomenal.

 

The I-V section could be simpler, I could drop the cascodes, I could use 2SK209s instead of BF862s. There are 3 in parallel both to handle the needed current (with room to space) as well as to further reduce current noise.

 

The discrete op amp filters could clearly be simpler... maybe the next version will be  If I were as brilliant as Nelson Pass I could do this all with a single jFet so I'm only 1/36th as smart as he is  

 

Power supplies: yep lots of independent floating power supplies. My goal outside of the DSC1 project is to develop a bullet proof isolation between the external world and the DSD signal going to those shift registers in the DAC. Lots of independent floating power supplies and I have a really cheap way to make them  (see DIYA dual bank floating power supply post) ... but that also means that any digital noise on the power lines to the digital board are isolated from the I-V section.

[jabbr]

28 minutes ago, 4est said:

And please do not think I mean this to disparage NP or yourself. He understood what he was doing   http://www.firstwatt.com/pdf/prod_m2_man.pdf    with the M2, and I assume you do as well.

Oh not at all -- I am using the M2 vs J2 simply as an analogy! and happy to discuss and defend my design issues. I think the digital board is fairly standard design wise -- assuming you want balanced, a ground & power plane with a bypass cap network, and a clock distribution network with similar propagation delays.

[jabbr]

33 minutes ago, Eclectico said:

In other points, what is the accuracy of the sine wave in the output of DSC1 dac in comparaison to 16 bits dac?

Output is 32 possible voltage levels against 65536 for 16 bits DAC...

What think about that?

 

The DSC1 DAC has an analog filter which follows the shift registers and I-V. The analog filter results in an approaching infinite number of output voltage levels.

[jabbr]

37 minutes ago, Eclectico said:

I agree and I see the power of DAC in accordance to time steps (abscissa for sine wave).

But let's look a little more on the ordinate.

Shift register are supplied by 3.3V, resistors are 8.2Kohm, at the end of I/v converter, the maximum output voltage can reach 6.4V. And the minimum output voltage available is 0.2Volt.

 

If we take example with Mola Mola dac for the maximum output voltage of 6.4V, min output voltage could be 0.025V.

258 combinations available.

 

In comparison if the output voltage should be at 0.1 Volt, we cannot obtain this value with DAC DSC1=> we can obtain 0V or 0.2V.

 

I discussed with T+A, they have only 2 shift registers but coefficient change with different resistors values.

IMO 1.5% of accuracy seems a little to just.

 

Not sure how relevant this is for a DSD DAC being fed DSD512 ... we are talking about different ways to filter out the 24.6mHz signal ...

 

No the DSC1 DAC is perfectly capable of 0.1 V output! or any other output. The audible range 20-20khz exists entirely in the DSD stream, and is there after the BCLK is filtered out. No the shift register FIR doesn't do this itself, think of it as a "prefilter" for the I-V section, for lack of a better term. But it does not replace the analog output filter and it is the analog output filter that provides smooth analog signals.

[jabbr]

@Eclectico work this out first without the shift register FIR, and just SDM stream and convince yourself that the 20-20kHz range gets out the DAC. Then and only then go back and add in the shift register FIR.

[jabbr]

1 hour ago, Eclectico said:

Jabbr, please explains how is it possible to reach 0.1V output if maximum output voltage is 6.4Volt with 33 voltage levels after the I/V converter?

IMO more there are voltage levels, less analog output filter is required.

 

 

I'm trying to help you understand this. What is your understanding about how an analog filter works on a digital waveform? Let's start very simple -- let's start with a digital signal that switches between 0 and 5volts every 1/1000 second. This is a 500 hz square wave. Now apply a low pass filter with a cutoff of 1khz. What does the output look like?

[jabbr]

2 hours ago, Eclectico said:

 

I dont have knowledge about this approch...

 

ok it will be a sine wave with smooth analogue voltages. this is how a DAC reconstructs a smooth (not stepped) analogue signal from digital. The analogue output filter is an anti-aliasing filter which converts the steps of the digital numbers into smoothly varying analogue voltages. if you have a "0" and then an interval later a "1", the output voltage smoothly rises from 0 v to 1 v. in this way there are not sharp voltage changes (the filter performs anti-aliasing)

[jabbr]

The behavior of an analog filter is described by the circuit. It is not described in terms of digital samples, rather the analog equation e.g. https://en.wikipedia.org/wiki/Butterworth_filter

 

the DSC1 uses a 4th order Sallen-Key low pass filter: https://en.wikipedia.org/wiki/Sallen–Key_topology

[jabbr]

1 hour ago, Ralf11 said:

I guess I got OT onto some form of predictive upsampling...

No prob, for our purposes here any type of upsampling is solidly in the HQPlayer domain, the DSC1 being a non-oversampling DAC. There are many advantages of digital filters such as crossovers, room correction etc but the very last anti-aliasing is done analogue which is why there is no issue with output quantization.

[jabbr]

38 minutes ago, HallmanLabs said:

I have a quick question about the DSC1 DAC (2016 model). I have two Rubycon Black Gate Non-polar caps I was hoping to use. I was told I can't use them in place of the two 100uF electrolytic caps towards the XMOS/Amanero pins, since that position needs polarized caps.

 

Then I realized that there are two other 100uF caps, the WIMA caps (coupling caps I believe). Is this a good use of capacitors as expensive as these? If not, any recommendations for where/how to use these non-polar Black Gates? Coupling is the most common way I see most non-polar caps being used.

 

I have upgraded 10k:10k transformers on the way, but I think there is room where the WIMA is soldered, comparing with my current 600:600 transformers.

 

Thanks for any info!

 

To be clear, can you post the schematic you are using because the dsc1 schematic does not have transformers.

[jabbr]

1 hour ago, HallmanLabs said:

I attached the DSC1 board I am using, don't have the schematic currently.

 

Whatever this DAC is, I object to calling it a DSC1 ... primarily because @Miska released the DSC1 as "Open Hardware" and this thing doesn't release a schematic is is required under the open hardware license.

 

The point of this thread is to use the open hardware design as a way for people to understand what the DAC is doing -- almost all DACs are closed design and folks can then argue about e.g. PCM vs DSD but who really knows. Without a schematic discussion of this DAC does not help us to understand the benefits of modifications such as transformers, various types of capacitors etc.

[jabbr]

Is this what we are talking about @ppy http://www.audiodesignguide.com/DSC1/index.html ?

 

If so, great, and I see the schematic