Mutec REF 10 Masterclock

[jabbr]

5 hours ago, Solstice380 said:

 

From a theoretical standpoint:

 

The receiver is triggered by the transition.  I don’t know if that trigger is a simple threshold level or a delta between 2 levels. 

 

@jabbr do you have knowledge of how a chip senses the clock signal to  trigger?

 

Depends on the chip and logic family. http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f01/Notes/chapter6.pdf

 

In the simplest situation the gates transition from "low" to "high" based on voltage thresholds. Transistors are fashioned into latches and flip flops. Data is latched into a chip via a clock:

 

In this example "ETL" or edge triggered logic:

http://web.ece.ucdavis.edu/~halasaad/Data/mwscs06.pdf

 

There are also differential logic families e.g. ECL.

 

https://patents.google.com/patent/US5900760

 

Again "edge triggered"

[jabbr]

12 hours ago, JohnSwenson said:

it should be possible for the manufacturers to optimize for phase noise only, thus giving us lower cost oscillators since they are not trying get say extremely low aging.

 

 

Q

 

and look at the cut, not “OXCO” 

 

12 hours ago, JohnSwenson said:

 

One other VERY important aspect about phase noise: comparing charts can ONLY be done if the frequencies are the same. The phase noise for an oscillator increacess by 6dBc/root Hz per octave of the oscillator frequency. Thus of you have plot for a 10 MHz oscillator and one for the same model oscillator at 20 MHz, the numbers will be 6 dBc/ root Hz higher. If you take that 20 MHz output and run it through a good flip flop, dividing the frequency by two, you will get the same phase noise plot as the 10MHz version.

 

Excellent point!