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How does re-clocking/re-sampling work?

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I often see DACs that use re-clocking and re-sampling to reduce input jitter (I'm thinking the Bryston BDA-1), but I'm wondering what happens with these processes. From my limited search, it seems that the inputted data is presented to the re-sampler which takes a sample at a fixed rate independently of the incoming rate. So, if the incoming signal has some jitter, the re-sampler will maybe get 95% of a 1 and call it a one, then 100% of a 0 and call it a zero, then 98% of a 0 etc. depending on the jitter of the incoming signal.


Is this the gist or completely off?


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If the incoming rate is different from the outgoing rate then we have rate adaption. Rate adaption will ultimately involve inserting/dropping packets (as buffers either fill or exhaust).


Reclockers, (e.g. the Antelope DA) assume the ingress = egress rate (or make the egress=ingress). They then lock onto the ingress signal clock and sample the ingress signal. Jitter may occur - often observed as an 'eye diagram'; samples are taken at the jittered clock time (edge). The egress recreates a 'clean' clock plus data.


Jitter should not be confused with either rate differences (ingress/egress) or long term instability of a clock.




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A resampler ( as used by e.g. Bel Canto, Benchmark ) uses an ASRC, as linked to above. This works by making no attempt to match the DAC clock with the source clock - the two are completely separate, and an ASRC manipulates the data to fit. This has a number of disadvantages, namely: The jitter ideally turns into wideband noise, so it hardly "goes away" or is "source impervious". Secondly, it is not guaranteed to be noise - often, due to difficulties measuring the ratio between clocks, or inadequacies producing filters for the infinite ratios, it may turn into correlated noise or distortion. Thirdly, the overriding filter response of the DAC is determined by the ASRC, so no opportunities for fancy filters.


A reclocker ( e.g. digital lens, most other DACs that don't use I2S ) uses a PLL to filter out the jitter - the clock of the DAC equals on average the clock of the source, and by averaging, the source jitter is attenuated - the degree to which it does this is a function of the quality of the source, and the quality of the PLL subsystem. The key advantage to a reclocker is that the data remains intact, but the timing is very dependent on the quality of the PLL...

There are many variations of the reclocker - e.g. Chord use a very slow PLL, with a big buffer to allow lots more averaging, but the cost of this is latency.


of course, some "reclocking" DACs are actually resamplers...


The ideal transport mechanism ( as I have mentioned before ) is where the important clock, in the DAC is in control of the source,



your friendly neighbourhood idiot


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